脉冲边沿检测设计

 1 `timescale 1ns / 1ps
 2 module MaiChongTest(
 3     input i_clk,
 4     input i_rst_n,
 5     input i_pulse,
 6     output o_rise_edge,
 7     output [1:0]r_pulse
 8     );
 9 reg[1:0] r_pulse;
10 wire r_pulse_invert;
11 always@(posedge i_clk)begin
12     if(!i_rst_n) r_pulse<=2'b00;
13     else r_pulse<={r_pulse[0],i_pulse};  
14    //等效下面这两行代码
15     //r_pulse[0]<=i_pulse;
16     //r_pulse[1]<=r_pulse[0];
17     end
18 assign r_pulse1_invert=~r_pulse[1];
19 assign o_rise_edge=r_pulse[0]& r_pulse1_invert;
20 endmodule

 1 `timescale 1ns / 1ps
 2 module TestBench();
 3 `define CLK_PERIORD        10        //时钟周期设置为10ns（100MHz）    
 4 //接口申明
 5 reg clk;
 6 reg rst_n;
 7 reg i_pulse;
 8 wire o_rise_edge;
 9 wire[1:0]r_pulse;
10     
11 //对被测试的设计进行例化
12 MaiChongTest my_tes(
13     .i_clk(clk),
14     .i_rst_n(rst_n),
15     .i_pulse(i_pulse),
16     .r_pulse(r_pulse[1:0]),
17     .o_rise_edge(o_rise_edge)
18     );    
19 //复位和时钟产生
20     //时钟和复位初始化、复位产生
21 initial begin
22     clk <= 0;
23     rst_n <= 0;
24     #50;
25     rst_n <= 1;
26 end
27     //时钟产生
28 always #(`CLK_PERIORD/2) clk = ~clk;    
29 initial begin
30     i_pulse<=1'b0;
31     @(posedge rst_n);    //等待复位完成
32     @(posedge clk);
33     repeat(5)begin
34        @(posedge clk);
35     end
36     #4
37     i_pulse<=1'b1;
38     repeat(5) begin
39         @(posedge clk);
40     end
41     #4
42     i_pulse<=1'b0;
43     repeat(5)begin
44        @(posedge clk);
45     end
46     $stop;
47 end
48 
49 endmodule