vhdl - 使用 vhdl 的 FIFO

Question

我正在为 fifo 编写 VHDL，但是当我模拟时没有输出？我无法在行为模拟中查看输出。就像 Data_in 中没有数据可供读取以写入 fifo 的输出一样。在我的代码中是写数据进入 FIFO 首先将数据推送到 DataIn 总线，然后将 WriteEn 输入选通一个时钟周期。

library IEEE;
        use IEEE.STD_LOGIC_1164.ALL;
        use IEEE.STD_LOGIC_UNSIGNED.ALL;
        use std.textio.all;
        use IEEE.NUMERIC_STD.ALL;


        entity fifo_mem is
        port (    clk : in std_logic;
                  reset : in std_logic;
                  enr : in std_logic;   
                  enw : in std_logic;   
                  data_in : in std_logic_vector (15 downto 0);     --input data
                  data_out : out std_logic_vector(15 downto 0);    --output data
                  fifo_empty : out std_logic;     
                  fifo_full : out std_logic   );
        end fifo_mem;
         architecture Behavioral of fifo_mem is
        type fifo_type is array(0 to 10) of bit_vector (15 downto 0);
        signal memory : fifo_type :=(others => (others => '0'));   
        signal readptr,writeptr : integer := 0;  --read and write pointers.
        signal empty,full : std_logic ;


     impure function InitRamFromFile (RamFileName : in string) return fifo_type is
        FILE RamFile : text is in RamFileName;
        variable RamFileLine : line;
        variable RAM : fifo_type;
        begin
        for I in 0 to 10  loop
        readline (RamFile, RamFileLine);
        read (RamFileLine, RAM(I));
        end loop;
        return RAM;
        end function;

     signal RAM : fifo_type :=InitRamFromFile("C:\Users\hp\Desktop\file\file1.txt");


begin
    fifo_empty <= empty;
    fifo_full <= full;

    process(Clk,reset)
    --this is the number of elements stored in fifo at a time.
    --this variable is used to decide whether the fifo is empty or full.
    variable num_elem : integer := 0;  
    begin
    if(reset = '1') then
        data_out <= (others => '0');
        empty <= '0';
        full <= '0';
        readptr <= 0;
        writeptr <= 0;
        num_elem := 0;
    elsif(rising_edge(Clk)) then
        if(enr = '1' and empty = '0') then  --read
            data_out <=to_stdlogicvector(RAM(readptr));
            readptr <= readptr + 1;      
            num_elem := num_elem-1;
        end if;
        if(enw ='1' and full = '0') then    --write
         RAM(writeptr)<= to_bitvector(data_in);
            writeptr <= writeptr +1;  
            num_elem := num_elem+1;
        end if;

         if(readptr = 10) then      --resetting read pointer.
            readptr <= 0;
        end if;
        if(writeptr = 10) then        --resetting write pointer.
            writeptr <= 0;
        end if; 
        --setting empty and full flags.
        if(num_elem = 0) then
            empty <= '1';
        else
            empty <= '0';
        end if;
        if(num_elem = 10) then
            full <= '1';
        else
            full <= '0';
        end if;
    end if; 
    end process;

    end Behavioral;

标签： vhdlfpga