vhdl - 具有两个输入和一个输出的 Mealy 机器的 VHDL 代码
问题描述
library ieee;
use ieee.std_logic_1164.all;
entity lab2exercise2 is
port
(
clk : in std_logic;
data_in1 : in std_logic;
data_in2 : in std_logic;
reset : in std_logic;
data_out : out std_logic_vector(1 downto 0)
);
end lab2exercise2;
architecture rtl of lab2exercise2 is
-- Build an enumerated type for the state machine
type state_type is (a, b, c, d);
-- Register to hold the current state
signal state : state_type;
signal clk_1hz : std_logic:= '0';
begin
process(clk)
variable counter : integer := 0;
variable edge_toggle : std_logic := '0';
begin
if (rising_edge(clk)) then
counter := counter + 1;
if (counter = 25000000) then
edge_toggle := not edge_toggle;
counter := 0;
end if;
end if;
clk_1hz <= edge_toggle;
end process;
process (clk_1hz, reset)
begin
if reset = '1' then
state<= a;
elsif (rising_edge(clk_1hz)) then
-- Determine the next state synchronously, based on
-- the current state and the input
case state is
when a=>
if((data_in1 = '0') & (data_in2 = '0'))then
state<=a;
if((data_in1 = '1') & (data_in2 = '0'))then
state<=a;
if((data_in1 = '1') & (data_in2 = '1')) then
state<=a;
else
state<=c;
end if;
when b=>
if ((data_in1 = '0') & (data_in2 = '0')) then
state<=a;
else if ((data_in1 = '1') & (data_in2 = '0'))then
state<=d;
else if ((data_in1 = '1') & (data_in2 = '1'))then
state<=d;
else
state<=c;
end if;
when c=>
if ((data_in1 = '1') & (data_in2 = '0')) then
state<=a;
else if ((data_in1 = '1') & (data_in2 = '1')) then
state<=a;
else if ((data_in1 = '0') & (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
when d=>
if ((data_in1 = '0') & (data_in2 = '1'))then
state<=d;
else if((data_in1 = '1') & (data_in2 = '0')) then
state<=d;
else if((data_in1 = '1') & (data_in2 = '1')) then
state<=d;
else
state<=b;
end if;
end case;
end if;
end process;
-- Determine the output based only on the current state
-- and the input (do not wait for a clock edge).
process (state, data_in1, data_in2)
begin
case state is
when a=>
if((data_in1 = '0') & (data_in2 = '0'))then
data_out<= "000";
if((data_in1 = '1') & (data_in2 = '0'))then
data_out<= "000";
if((data_in1 = '1') & (data_in2 = '1')) then
data_out<= "000";
else
data_out<= "010";
end if;
when b=>
if ((data_in1 = '0') & (data_in2 = '0')) then
data_out<= "000";
else if ((data_in1 = '1') & (data_in2 = '0'))then
data_out<= "011";
else if ((data_in1 = '1') & (data_in2 = '1'))then
data_out<= "011";
else
data_out<= "010";
end if;
when c=>
if ((data_in1 = '1') & (data_in2 = '0')) then
data_out<= "100";
else if ((data_in1 = '1') & (data_in2 = '1')) then
data_out<= "100";
else if ((data_in1 = '0') & (data_in2 = '1')) then
data_out<= "111";
else
data_out<= "101";
end if;
when d=>
if ((data_in1 = '0') & (data_in2 = '1'))then
data_out<= "111";
else if((data_in1 = '1') & (data_in2 = '0')) then
data_out<= "111";
else if((data_in1 = '1') & (data_in2 = '1')) then
data_out<= "111";
else
data_out<= "111";
end if;
end case;
end process;
end rtl;
这是我的代码。我尝试运行它,但总是在“当 b=>、当 c=> 和当 d=>”和“结束进程”行出现错误 10500。如何正确运行代码?顺便说一句,这是一台 Mealy 机器,并以此为基础。具有两个 D 触发器 A 和 B、两个输入 x 和 y 的时序电路;一个输出 z 由以下下一状态和输出方程指定。
A(t +1)=xy’ +xB
B(t +1)=xA+Xb’
z=A
解决方案
VHDLif
语句的一般语法是:
if condition1 then
...
elsif condition2 then
...
elsif condition3 then
...
else
...
end if;
如果你使用else if
而不是elsif
,你有几个嵌套if
语句,你需要尽可能多的end if
:
if condition1 then
...
else if condition2 then
...
end if;
end if;
笔记:
- 正确缩进代码使其更具可读性(对您和 StackOverflow 读者而言),更易于调试和维护。
- 在没有显示错误消息的情况下询问您为什么会收到错误并不是获得帮助的最佳方式。错误消息通常在这里帮助您(或 StackOverflow 读者)了解问题所在。掩盖它就像告诉医生它很痛,但不告诉他在哪里。
- 您也许可以访问“提问”部分,以更好地了解如何提出好的问题,尤其是什么是最小、完整和可验证示例 (MCVE)。
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