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vhdl - 不支持的属性错误

问题描述

我编写了一个 VHDL 函数vectorize()来将 std_logic_vector 数组（slv_1d_array_type在我的代码中输入）转换为 std_logic_vector。

Vivado 2018.2[Synth 8-5882] found unsupported attribute ["test_top.vhd":41]使用以下示例生成此错误。我已将 Vivado 配置为使用 VHDL-2008。

如何使这些'length属性起作用以避免传递数组大小？

-- Libraries
------------

library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------

entity test_top is
    generic(
        DATA_WIDTH : positive := 32
    );

    port(
        O_DATA    : out std_logic_vector(DATA_WIDTH - 1 downto 0)
    );
end entity test_top;

------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------

architecture rtl of test_top is

    --------------------------------------------------------------------------------------------------------------------
    -- Types definition
    --------------------------------------------------------------------------------------------------------------------

    type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.

    --------------------------------------------------------------------------------------------------------------------
    -- Functions declaration
    --------------------------------------------------------------------------------------------------------------------

    function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
        variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY'element'length - 1 downto 0);
    begin
        for i in SLV_1D_ARRAY'range loop
            vector_v(SLV_1D_ARRAY'element'length * (i + 1) - 1 downto SLV_1D_ARRAY'element'length * i) := SLV_1D_ARRAY(i);
        end loop;

        return vector_v;
    end function vectorize;

    --------------------------------------------------------------------------------------------------------------------
    -- Signals declaration
    --------------------------------------------------------------------------------------------------------------------

    signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));

begin

    O_DATA <= vectorize(data_r);

end architecture rtl;

标签： vhdlvivadoregister-transfer-level

解决方案

根据UG901第 6 章“ VHDL-2008 语言支持”，没有提及'element属性。所以官方不支持。

来自 Xilinx 论坛的这个帖子声明它受到严重支持，并已从 Vivado 2016.3 开始删除。

但是，上面的代码示例被 ModelSim 10.6c 接受。

@Juergen 提供的解决方法在 Vivado 2018.2 中按预期工作。这是示例的更新版本，包括解决方法：

-- Libraries
------------

library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------

entity test_top is
    generic(
        DATA_WIDTH : positive := 32
    );

    port(
        O_DATA    : out std_logic_vector(DATA_WIDTH - 1 downto 0)
    );
end entity test_top;

------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------

architecture rtl of test_top is

    --------------------------------------------------------------------------------------------------------------------
    -- Types definition
    --------------------------------------------------------------------------------------------------------------------

    type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.

    --------------------------------------------------------------------------------------------------------------------
    -- Functions declaration
    --------------------------------------------------------------------------------------------------------------------

    function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
        variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length - 1 downto 0);
    begin
        for i in SLV_1D_ARRAY'range loop
            vector_v(SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * (i + 1) - 1 downto SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * i) := SLV_1D_ARRAY(i);
        end loop;

        return vector_v;
    end function vectorize;

    --------------------------------------------------------------------------------------------------------------------
    -- Signals declaration
    --------------------------------------------------------------------------------------------------------------------

    signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));

begin

    O_DATA <= vectorize(data_r);

end architecture rtl;

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