vhdl - 在 VHDL 代码中启动时，ModelSim 中的信号部分为 U

Question

视窗 10

Quartus II 64 位版本 13.0.1

ModelSim 修订：2012.11 日期：2012 年 11 月 2 日

VHDL代码

“运行模拟工具”->“门级模拟”

我有以下代码，该过程由时钟（gclk0）和复位信号（fpga_resetn）控制。

我的问题是，在 set_regs_resample 中，为什么位 1 'U'，位 0 和位 2 是 0，正如预期的那样。

当信号 fpga_resetn 为低时，set_regs_resample 中的所有位不应该为零吗？

VHDL代码

SIGNAL set_regs_resample                 : STD_LOGIC_VECTOR(2 DOWNTO 0);


  -- purpose: to generate the internal control registers
  -- type   : sequential
  -- inputs : gclk0, fpga_resetn
  -- outputs: 
  gen_internal_regs : PROCESS (gclk0, fpga_resetn) IS
  BEGIN  -- PROCESS gen_internal_regs
    IF fpga_resetn = '0' THEN           -- asynchronous reset (active low)
      reg_adr            <= (OTHERS => '0');
      res_set_regs       <= '1';
      set_regs_resample  <= "000";
      version_vector     <= TO_STD_LOGIC_VECTOR(version_str);
      version_pntr       <= 0;
      data_available_ver <= '0';
    ELSIF rising_edge(gclk0) THEN       -- rising clock edge

vsim 文件

# vsim work.bomill_fpga

restart -force

delete wave *

add wave -position insertpoint  sim:/bomill_fpga/gclk0
add wave -position insertpoint  sim:/bomill_fpga/fpga_resetn
add wave -position insertpoint  sim:/bomill_fpga/set_regs_resample
add wave -position insertpoint   sim:/bomill_fpga/res_set_regs/regout


force /bomill_fpga/fpga_resetn 0 0, 1 { 450 ns }
force -deposit /bomill_fpga/gclk0 1 0, 0 {83 ns} -repeat 167 ns

run 1.2 us

信号的屏幕转储

ModelSim 成绩单窗口

VSIM 3> do ADC_Simulation.do
# ** Warning: Design size of 1 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# ** Warning: (vsim-8683) Uninitialized out port /bomill_fpga/altera_internal_jtag/tdo has no driver.
# 
# This port will contribute value (U) to the signal network.
# 
# ** Warning: (vsim-8683) Uninitialized out port /bomill_fpga/altera_internal_jtag/tmsutap has no driver.
# 
# This port will contribute value (U) to the signal network.
# 
# ** Warning: (vsim-8683) Uninitialized out port /bomill_fpga/altera_internal_jtag/tckutap has no driver.
# 
# This port will contribute value (U) to the signal network.
# 
# ** Warning: (vsim-8683) Uninitialized out port /bomill_fpga/altera_internal_jtag/tdiutap has no driver.
# 
# This port will contribute value (U) to the signal network.
# 

标签： vhdlmodelsim