clash - 如何实现 Clash readNew 亚稳态解决方法？

Question

如何正确使用readNew？

一个包含两个模块的最小示例，它们只读取和写入asyncRam：

顶层.hs

module TopLevel where

import Clash.Prelude
import LowerLevel

topEntity 
  :: Clock System Source
  -> Reset System Asynchronous
  -> Signal System (Unsigned 5)
  -> Signal System (Maybe (Unsigned 5, BitVector 5))
  -> Signal System (BitVector 5)
topEntity = exposeClockReset topLevel

topLevel :: HiddenClockReset dom gated sync
         => Signal dom (Unsigned 5)
         -> Signal dom (Maybe (Unsigned 5, BitVector 5))
         -> Signal dom (BitVector 5)
topLevel rdAddr wrM = lowerLevel rdAddr wrM

低级.hs

module LowerLevel where

import Clash.Prelude

lowerLevel :: HiddenClockReset dom gated sync
           => Signal dom (Unsigned 5)
           -> Signal dom (Maybe (Unsigned 5, BitVector 5))
           -> Signal dom (BitVector 5)
lowerLevel rdAddr wrM = readNew (asyncRam d32) rdAddr wrM

目前，当我编译此代码时，我收到亚稳态警告（尽管它是成功的）：

Compiling: TopLevel.topEntity LowerLevel.$sreadNew20998 (::
GHC.Classes.IP   rst   (Clash.Signal.Internal.Reset
     (Clash.Signal.Internal.Dom system 10000)
     Clash.Signal.Internal.Asynchronous)
-> GHC.Classes.IP
     clk
     (Clash.Signal.Internal.Clock
        (Clash.Signal.Internal.Dom system 10000)
        Clash.Signal.Internal.Source)
-> Clash.Signal.Internal.Clock
     (Clash.Signal.Internal.Dom system 10000)
     Clash.Signal.Internal.Source
-> Clash.Signal.Internal.Signal
     (Clash.Signal.Internal.Dom system 10000)
     (Clash.Sized.Internal.Unsigned.Unsigned 5)
-> Clash.Signal.Internal.Signal
     (Clash.Signal.Internal.Dom system 10000)
     (GHC.Base.Maybe
        (GHC.Tuple.(,)
           (Clash.Sized.Internal.Unsigned.Unsigned 5)
           (Clash.Sized.Internal.BitVector.BitVector 5)))
-> Clash.Sized.Internal.BitVector.BitVector 5) has potentially dangerous meta-stability issues:

The following clocks:
* GHC.Classes.IP   clk   (Clash.Signal.Internal.Clock
     (Clash.Signal.Internal.Dom system 10000)
     Clash.Signal.Internal.Source)
* Clash.Signal.Internal.Clock   (Clash.Signal.Internal.Dom system 10000)   Clash.Signal.Internal.Source belong to the same clock domain
and should be connected to the same clock source in order to prevent
meta-stability issues.

我做了一些研究，发现了这个 google group answer。我很确定这是我应该做的，但我不确定如何实施。

asyncRam clk d32如帖子中所述，我将如何内联？我如何获得“免费时钟”？我正在尝试readNew来自Clash.Explicit.Prelude（不成功），但我不明白为什么我不能只使用Prelude版本。我认为可能有一些需要，exposeClockReset但从我读过的内容来看，似乎有来自同一域的两个时钟被用来规避亚稳态警告？请澄清，谢谢！

更新：这是一个已知问题。有人告诉我现在可以忽略编译器警告。

标签： clash