vhdl - 赛灵思 ISE：未声明

Question

我正在为 vga 控制器编写代码，在顶部模块 Xilinx ISE 中给出了这个错误：

<vga> 未声明

虽然我已将端口映射到顶部模块

代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vga_controller is
port(mclk : in std_logic;
button: in std_logic;
hs: out std_logic;
vs: out std_logic;
red: out std_logic_vector (3 downto 0);
green: out std_logic_vector (3 downto 0);
blue: out std_logic_vector (3 downto 0)
);
end vga_controller;

architecture vga_controller of vga_controller is
signal clk25,clr,video :std_logic;
signal hc,vc:std_logic_vector (9 downto 0);
begin
clr<=button;
M2: vga
port map (clk25,button,hs,vs,hc,vc,video);
M3: vga_plotter
port map(hc,vc,video,red,green,blue);
end vga_controller;

标签： vhdlfpgaxilinxvga

Answer 1

您没有 VGA 组件的组件声明。