vhdl - 状态机和无符号信号

问题描述

我制作的一个相当简单的状态机有一些问题。无论我做什么，信号 startS1、startS2、enS 和 mS 在模拟中总是保持无符号状态，即使我按下了复位按钮，我也不知道为什么。混合中有一个组件，但我确实测试了该组件并且它工作得很好。我希望你能帮帮我！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity machine_etat is
generic (N_bit : integer := 8);
Port ( LOAD : in STD_LOGIC_VECTOR (N_bit-1 downto 0);
       RESET : in STD_LOGIC;
       START : in STD_LOGIC;
       CLK : in STD_LOGIC;
       OUTPUT : out STD_LOGIC_VECTOR (N_bit-1 downto 0));
end machine_etat;

architecture Behavioral of machine_etat is

TYPE machine is (IddleT, DepartT, LoadT, ShiftT, EndT);
SIGNAL Etat1, Etat2 : machine:= IddleT;

SIGNAL mS: STD_LOGIC_VECTOR (1 downto 0);
SIGNAL enS : STD_LOGIC;
SIGNAL outputS : STD_LOGIC_VECTOR (N_bit-1 downto 0);

component Reg_decal is
generic (N_bit : integer := N_bit);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
EN : in STD_LOGIC;
M : in STD_LOGIC_VECTOR (1 downto 0);
LOAD : in STD_LOGIC_VECTOR (N_bit-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (N_bit-1 downto 0));
end component;

SIGNAL startS1, startS2 : STD_LOGIC;

begin

OUTPUT <= outputS;


Reg_dec: Reg_decal 
    generic map (N_bit => N_bit)
    port map (CLK => CLK,
              RESET => RESET,
              EN => enS,
              M => mS,
              LOAD => LOAD,
              OUTPUT => outputS);

Machine1: process (CLK)
begin
    if RESET = '1' then
        enS <= '0';
        mS <= "00";
        startS1 <= '0';
        startS2 <= '0';
        Etat1 <= IddleT;
    elsif rising_edge(CLK) then
        CASE Etat1 is
            WHEN IddleT =>
                if startS1 = '1' OR START = '1' then
                    Etat1 <= DepartT;
                 else
                    Etat1 <= IddleT;
                 end if;

            WHEN DepartT =>
                Etat1 <= LoadT;
                startS1 <= '0';
            WHEN LoadT =>
                mS <= "11";
                enS <= '1';
                Etat1 <= ShiftT;

            WHEN ShiftT =>
                mS <= "00";
                Etat1 <= EndT;

            WHEN EndT =>
                enS <= '0';
                startS2 <= '1';
                Etat1 <= IddleT;

            WHEN Others =>
                Etat1 <= IddleT;
        end CASE; 
   end if;
end process;

Machine2: process (CLK)

begin
if RESET = '1' then
    Etat2 <= IddleT;
elsif rising_edge(CLK) then
            CASE Etat2 is
                WHEN IddleT =>
                    if startS2 = '1' then
                        Etat2 <= DepartT;
                    else
                        Etat2 <= IddleT;
                    end if;

                WHEN DepartT =>
                    startS2 <= '0';
                    Etat2 <= LoadT;

                WHEN LoadT =>
                    enS <= '1';
                    Etat2 <= ShiftT;

                WHEN ShiftT =>
                    mS <= "01";
                    Etat2 <= EndT;

                WHEN EndT =>
                    Etat2 <= IddleT;
                    startS1 <= '1';
                WHEN Others =>
            end CASE;
        end if;
    end process;


end Behavioral;

标签： vhdl

vhdl - 状态机和无符号信号

问题描述

解决方案

推荐阅读