vhdl - 如何修复 VHDL 中的“U”输出

Question

我的代码需要帮助。我为一个简单的项目编写了该代码，现在当我尝试对其进行测试时，输出全部为 U。该代码用于门，当徽章变为 1 时，您有 3 次尝试发送正确的开门密码。当徽章变为 0 时，门关闭。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Porta is
    Port ( Badge : in  STD_LOGIC;
           Comb : in  STD_LOGIC_VECTOR(15 downto 0);
           Lock : out  STD_LOGIC);
end Porta;

architecture Behavioral of Porta is

signal pass: STD_LOGIC_VECTOR(15 downto 0) := "1001100110011001";
signal tent: unsigned(1 downto 0) := "00"; --Tent
signal l: STD_LOGIC := '0';

begin

p_badge: process(Badge)
begin
    report "Process Badge!";
    if Badge = '1' then
        report "Process Badge dentro IF=1";
        tent <= (others => '0');
    else
        l <= '0';
    end if;
end process p_badge;

--Contatore tentativi e controllo combinazione
p_pass: process(Comb)
begin
    report "Process Confirm!";
    if tent /= "11" then
        if Comb = pass then
            report "Process Confirm, Comb=pass";
            l <= '1';
            tent <= (others => '0');
        elsif Comb /= pass then
            report "Process Confirm, Comb!=pass";
            tent <= tent+"01";
        end if;
    else
    report "tent=11";
    end if;
end process p_pass;

--Processo per il lock
p_lock: process(l)
begin
    report "Process LOCK!!";
    if l = '1' then
        Lock <= '1';
    else
        Lock <= '0';
    end if;
end process p_lock;

end Behavioral;

编辑：我简化了代码，但 Lock 的值没有显示在 ISIM 中，并且多次发生错误： Instance /porta_tb4/uut/ : Warning: NUMERIC_STD."/=": 检测到元值，返回 TRUE。

我发布了我创建的简单测试

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Porta_tb4 IS
END Porta_tb4;

ARCHITECTURE behavior OF Porta_tb4 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Porta
    PORT(
         Badge : IN  std_logic;
         Comb : IN  std_logic_vector(15 downto 0);
         Lock : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal Badge : std_logic := '0';
   signal Comb : std_logic_vector(15 downto 0) := (others => '0');

    --Outputs
     signal Lock : std_logic;

   BEGIN

   uut: Porta PORT MAP (
          Badge => Badge,
          Comb => Comb,
          Lock => Lock
        );


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
        wait for 100 ns;    
        Badge <= '1';
        wait for 100 ns;
        Comb <= "1001100110010011";
        wait for 100 ns;
        Comb <= "1001100110110011";
        wait for 100 ns;
        Comb <= "1001101110010011";
        wait for 100 ns;
        Comb <= "1011101110010011";
        wait for 100 ns;
        Badge <= '1';
        wait for 100 ns;
        Comb <= "1001100110011001";
        wait for 100 ns;
        Badge <= '0';
    -- insert stimulus here 

   wait;
   end process;

END;

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