memory - 在设计 8 x 32 内存时，当块后端口映射导致未知输出时，2d 信号导致生成块

Question

请帮助我，我正在尝试使用结构建模开发 8 x 32 位读/写内存。我开发了以下模块

0) output_array_types (包)

1) register_32_bit

2) dmux_1by8

3) mux_8by1 (32 位宽)

4）xor_1bit（与我的问题无关）

5）data_memory_2pow3_32（这是我的问题发生的地方）

所有模块都经过独立测试，除了主文件（第 5 个）外，它们都可以工作，由于对 vhdl 语法缺乏了解，主文件中使用的 mux_8by1 为 2d 信号输入（包含所有 8 个寄存器值）提供未知输出内存），多路复用器应该根据在选择行断言的地址从中选择行，以获取该行值作为输出。

我在下面附上了代码和输出。请帮助我在主文件中哪里出错了，我特别怀疑主文件中的“unit11”。

提前致谢

output_array_types.vhd

library ieee;

use ieee.std_logic_1164.all;

package output_array_types is

    type op_arr is array(0 to 7) of STD_LOGIC;
    type op_arr_32bit is array(0 to 7) of STD_LOGIC_VECTOR(31 downto 0);

end package output_array_types;

register_32_bit.vhd

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity register_32_bit is
    port(
        rst: in STD_LOGIC;
        enable: in STD_LOGIC;
        load: in STD_LOGIC;
        data_in: in STD_LOGIC_VECTOR(31 downto 0);
        data_out: out STD_LOGIC_VECTOR(31 downto 0)
    );
end register_32_bit;

architecture behavioral of register_32_bit is

begin
     process(rst,enable,load)
     begin
          if (rst = '0') then
                data_out<=STD_LOGIC_VECTOR(to_unsigned(0, 32));
          elsif (enable = '1') then
                if (load = '1') then
                      data_out<=data_in;
                end if;
          end if;
     end process;
end behavioral;

dmux_1by8.vhd

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.output_array_types.all;

entity dmux_1by8 is
    port(data_in: in STD_LOGIC;
        sel: in STD_LOGIC_VECTOR(2 downto 0);
        data_out: out op_arr
    );
end dmux_1by8;

architecture behavioral of dmux_1by8 is
begin
    process(sel)
    begin
        data_out<= (others =>'0');
        data_out(to_integer(unsigned(sel)))<= data_in;
    end process;
end behavioral;

mux_8by1.vhd

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.output_array_types.all;

entity mux_8by1 is
    port(data_in: in op_arr_32bit;
        sel: in STD_LOGIC_VECTOR(2 downto 0);
        data_out: out STD_LOGIC_VECTOR(31 downto 0)
    );
end mux_8by1;

architecture behavioral of mux_8by1 is

begin
    process(sel)
    begin
        data_out<= data_in(to_integer(unsigned(sel)));
    end process;
end behavioral;

xor_1bit.vhd

library ieee;

use ieee.std_logic_1164.all;

entity xor_1bit is
    port(op: in STD_LOGIC_VECTOR(1 downto 0);
        result: out STD_LOGIC
    );
end xor_1bit;

architecture behavioral of xor_1bit is
begin
    process(op)
    begin
        if(op = "00") then
        result<= '0';
        elsif(op = "01") then
        result<= '1';
        elsif(op = "10") then
        result<= '1';
        elsif(op = "11") then
        result<= '0';
        end if;
    end process;
end behavioral;

data_memory_2pow3_32.vhd

library ieee,work;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.output_array_types.all;


entity data_memory_2pow3_32 is
    port(mem_write: in STD_LOGIC := '1';
        mem_read: in STD_LOGIC := '0';
        address: in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
        write_data: in STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
        read_data: out STD_LOGIC_VECTOR(31 downto 0);
        mem_rst: in STD_LOGIC := '1'
    );
end data_memory_2pow3_32;

architecture structural of data_memory_2pow3_32 is
    component register_32_bit is
    port(
        rst: in STD_LOGIC;
        enable: in STD_LOGIC;
        load: in STD_LOGIC;
        data_in: in STD_LOGIC_VECTOR(31 downto 0);
        data_out: out STD_LOGIC_VECTOR(31 downto 0)
    );
    end component;

    component dmux_1by8 is
    port(data_in: in STD_LOGIC;
        sel: in STD_LOGIC_VECTOR(2 downto 0);
        data_out: out op_arr
    );
    end component;

    component mux_8by1 is
    port(data_in: in op_arr_32bit;
        sel: in STD_LOGIC_VECTOR(2 downto 0);
        data_out: out STD_LOGIC_VECTOR(31 downto 0)
    );
    end component;

    component xor_1bit is
    port(op: in STD_LOGIC_VECTOR(1 downto 0);
        result: out STD_LOGIC
    );
    end component;


signal dmux_1by8_out : op_arr;
signal mux_8by1_in : op_arr_32bit;
signal read_xor_write: STD_LOGIC;
signal mux_8by1_out: STD_LOGIC_VECTOR(31 downto 0);
alias address_0to2 is address(2 downto 0);

begin
    unit0: xor_1bit port map(op(0) => mem_write, op(1) => mem_read, result => read_xor_write);

    unit1: dmux_1by8 port map(data_in => mem_write, sel => address_0to2, data_out => dmux_1by8_out);

    unit: for i in 0 to 7 generate
        unit2to9: register_32_bit port map(rst => mem_rst ,enable => read_xor_write ,load => dmux_1by8_out(i),data_in => write_data,data_out => mux_8by1_in(i));
        end generate;

    --Till here everything works, after this when the mux_8by1_in (2d signal
    --array) is mapped to the mux_8by1 below, the output read_data 
    --turns out to be unknown whereas there's no problem in mux_8by1 module 
    --when tested independently. Hence there must be some erroneous mapping 
    --being performed here.

    unit11: mux_8by1 port map(data_in => mux_8by1_in, sel => address_0to2, data_out => read_data);

end structural;

[1 [我在 modelsim 中得到的输出]]：https ://i.stack.imgur.com/McvV4.png

[2 [我正在使用的内存架构图]]：https ://i.stack.imgur.com/hJb7n.jpg

标签： memorymultidimensional-arrayvhdl