vhdl - tic tac toe vhdl 学生项目

Question

问题是输出与 ifs 不匹配。我想要，例如行 A，如果一切都是 1，则输出应该是 11。但它不是

library ieee;  
 use ieee.std_logic_1164.all;  
 use ieee.numeric_std.all;  

 entity galo_ports is  
  port( LinA : in unsigned(2 downto 0); 
    LinB : in unsigned(2 downto 0);
    LinC : in unsigned(2 downto 0);

    output : out unsigned(1 downto 0)); 
 end galo_ports;

ARCHITECTURE main OF galo_ports IS
SIGNAL values: std_logic_vector(1 downto 0);
SIGNAL condition1A: boolean;
SIGNAL condition2A: boolean;
SIGNAL condition3A: boolean;
SIGNAL condition1B: boolean;
SIGNAL condition2B: boolean;
SIGNAL condition3B: boolean;
SIGNAL condition1C: boolean;
SIGNAL condition2C: boolean;
SIGNAL condition3C: boolean;
SIGNAL condition1COL1: boolean;
SIGNAL condition2COL1: boolean;
SIGNAL condition3COL1: boolean;
SIGNAL condition1COL2: boolean;
SIGNAL condition2COL2: boolean;
SIGNAL condition3COL2: boolean;
SIGNAL condition1COL3: boolean;
SIGNAL condition2COL3: boolean;
SIGNAL condition3COL3: boolean;
SIGNAL condition1DIG1: boolean;
SIGNAL condition2DIG1: boolean;
SIGNAL condition3DIG1: boolean;
SIGNAL condition1DIG2: boolean;
SIGNAL condition2DIG2: boolean;
SIGNAL condition3DIG2: boolean;
BEGIN
values <= "10";

--CONDIÇÃOES:
--LINHA 1
condition1A <= LinA(0) = LinA(1) and LinA(1) = LinA(2);
condition2A <= LinA(0) = values(0) or LinA(0) = values(1);
condition3A <= LinA(0) = values(1);
--LINHA 2
condition1B <= LinB(0) = LinB(1) and LinB(1) = LinB(2);
condition2B <= LinB(0) = values(0) or LinB(0) = values(1);
condition3B <= LinB(0) = values(1);
--LINHA 3
condition1C <= LinC(0) = LinC(1) and LinC(1) = LinC(2);
condition2C <= LinC(0) = values(0) or LinC(0) = values(1);
condition3C <= LinC(0) = values(1);
--COLUNA 1
condition1COL1 <= LinA(0) = LinB(0) and LinB(0) = LinC(0);
condition2COL1 <= LinA(0) = values(0) or LinA(0) = values(1);
condition3COL1 <= LinA(0) = values(1);
--COLUNA 2
condition1COL2 <= LinA(1) = LinB(1) and LinB(1) = LinC(1);
condition2COL2 <= LinA(1) = values(0) or LinA(1) = values(1);
condition3COL2 <= LinA(1) = values(1);
--COLUNA 3
condition1COL3 <= LinA(2) = LinB(2) and LinB(2) = LinC(2);
condition2COL3 <= LinB(2) = values(0) or LinA(2) = values(1);
condition3COL3 <= LinB(2) = values(1);
--DIAGONAL 1
condition1DIG1 <= LinA(0) = LinB(1) and LinB(1) = LinC(2);
condition2DIG1 <= LinA(0) = values(0) or LinA(0) = values(1);
condition3DIG1 <= LinA(0) = values(1);
--DIAGONAL 2
condition1DIG2 <= LinA(2) = LinB(1) and LinB(1) = LinC(0);
condition2DIG2 <= LinA(2) = values(0) or LinA(2) = values(1);
condition3DIG2 <= LinA(2) = values(1);
    PROCESS(LinA, LinB, LinC)
    BEGIN
        --LINHA 1
        IF condition1A=TRUE and condition2A=TRUE and condition3A=TRUE THEN output <= "11";
        END IF;
        --LINHA 2
        IF (condition1B) and (condition2B) and (condition3B) THEN output <= "11"; ELSE output <="00";
        END IF;
        --LINHA 3
        IF condition1C and condition2C and condition3C THEN output <= "11";
        END IF;
        --COLUNA 1
        IF condition1COL1 and condition2COL1 and condition3COL1 THEN output <= "11";
        END IF;
        --COLUNA 2
        IF condition1COL2 and condition2COL2 and condition3COL2 THEN output <= "11";
        END IF;
        --COLUNA 3
        IF condition1COL3 and condition2COL3 and condition3COL3 THEN output <= "11";
        END IF;
        --DIAGONAL 1
        IF condition1DIG1 and condition2DIG1 and condition3DIG1 THEN output <= "11";
        END IF;
        --DIAGONAL 2
        IF condition1DIG2 and condition2DIG2 and condition3DIG2 THEN output <= "11";
        END IF;

    END PROCESS;
END main;

游戏包含一个 9 个位置的棋盘，每个玩家在一个免费的房子里移动，用“0”（玩家 A）或“1”（玩家 B）标记它。

胜利将授予能够水平、垂直或对角放置 3 个“0”或 3 个“1”的玩家。

解决方案应该在退出时显示哪个玩家获胜或平局 - 如果没有玩家可以实现定义的目标。

标签： vhdl

Answer 1

我删除了我原来的答案，因为@pm101 指出它完全偏离了轨道。

编译您的设计后，警告说明了明显的原因：

galo_ports.vhd(142) 处的 VHDL Process Statement 警告：在 Process Statement 中读取信号“condition1A”，但不在 Process Statement 的敏感度列表中

当、或变化时，conditionXXX信号的值会更新。但是，该过程是同时执行的，并且这些条件信号的值尚未更新。如果您正在模拟设计，您会看到lags 的值：它会在输入更改时更新，但它可能会显示之前输入的游戏结果。linAlinBlinCoutput

修复过程敏感度列表以包含所有条件信号。conditionXXX然后，当您的信号发生变化并且条件表达式被正确评估时，该过程将被执行。所以像：

PROCESS(condition1A, condition2A, condition3A, condition1B, condition2B, condition3B, condition1C, condition2C, condition3C, condition1COl1, condition2COL1, condition3COL1, condition1COL2, condition2COL2, condition3COL2, condition1COL3, condition2COL3, condition3COL3, condition1DIG1, condition2DIG1, condition3DIG1, condition1DIG2, condition2DIG2, condition3DIG2)

此外，我会将该条件列表包装到一个IF带有ELSIF语句的块中。然后在ELSE声明中，您还必须定义output没有获胜者时的值（或 0 是获胜者）：

  --LINHA 1
  IF condition1A=TRUE and condition2A=TRUE and condition3A=TRUE THEN output <= "11";
  --LINHA 2
  ELSIF (condition1B) and (condition2B) and (condition3B) THEN output <= "11";
  --LINHA 3
  ELSIF condition1C and condition2C and condition3C THEN output <= "11";
  --COLUNA 1
  ELSIF condition1COL1 and condition2COL1 and condition3COL1 THEN output <= "11";
  --COLUNA 2
  ELSIF condition1COL2 and condition2COL2 and condition3COL2 THEN output <= "11";
  --COLUNA 3
  ELSIF condition1COL3 and condition2COL3 and condition3COL3 THEN output <= "11";
  --DIAGONAL 1
  ELSIF condition1DIG1 and condition2DIG1 and condition3DIG1 THEN output <= "11";
  --DIAGONAL 2
  ELSIF condition1DIG2 and condition2DIG2 and condition3DIG2 THEN output <= "11";
  ELSE output <= "00"; -- 0 wins or no winner. 
  END IF;