vhdl - JK 4-bit up counter - reset on 1010 not working

Question

JK flip flop code :

library ieee;
use ieee.std_logic_1164.all;

ENTITY JK IS PORT
(
    J,K,clk,rst,set : IN std_logic;
    Q, nQ : OUT std_logic
);
END JK;


ARCHITECTURE arch OF JK IS
    SIGNAL Qtemp : std_logic := '0';
    SIGNAL nQtemp : std_logic := '1';
BEGIN

    Q <= Qtemp;
    nQ <= nQtemp;

    jk_process : PROCESS(clk,rst,set)
    BEGIN
        if(rst = '1') then
            Qtemp <= '0';
            nQtemp <= '1';

        elsif(set = '1') then
            Qtemp <= '1';
            nQtemp <= '0';

        elsif(clk'event and clk = '1') then
            if(J = '0' and K = '0') then
                NULL;
            elsif(J = '1' and K = '0') then
                Qtemp <= '1';
                nQtemp <= '0';
            elsif(J = '0' and K = '1') then
                Qtemp <= '0';
                nQtemp <= '1';
            elsif(J = '1' and K = '1') then
                Qtemp <= not Qtemp;
                nQtemp <= not nQtemp;
            end if;
        end if;
    END PROCESS;
END arch;

Counter code :

library ieee;
use ieee.std_logic_1164.all;

ENTITY brojilo IS PORT
(
    clk : IN std_logic;
    Q_vector : OUT std_logic_vector(3 downto 0) := "0000";
    Q_negated_vector : OUT std_logic_vector(3 downto 0) := "0000";
    and_in_values : OUT std_logic_vector(3 downto 0) := "0000";
    and_out_value : OUT std_logic := '0'
);
END brojilo;

ARCHITECTURE arch OF brojilo IS
    SIGNAL int_clk_b0_b1 : std_logic := '0';
    SIGNAL int_clk_b1_b2 : std_logic := '0';
    SIGNAL int_clk_b2_b3 : std_logic := '0';

    SIGNAL Q_temp_vector : std_logic_vector(3 downto 0) := "0000";
    SIGNAL Q_temp_negated_vector : std_logic_vector(3 downto 0) := "0000";

    SIGNAL and_vector : std_logic_vector(3 downto 0) := "0000";
    SIGNAL and_out_reset : std_logic := '0';
BEGIN   

    and_out_reset <= and_vector(0) and and_vector(1) and and_vector(2) and and_vector(3);
    and_out_value <= and_out_reset;

    b0 : ENTITY work.JK port map(J => '1', K => '1', clk => clk, rst => and_out_reset, set => '0', Q => Q_temp_vector(0), nQ => Q_temp_negated_vector(0));
    int_clk_b0_b1 <= Q_temp_negated_vector(0);

    b1 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b0_b1, rst => and_out_reset, set => '0', Q => Q_temp_vector(1), nQ => Q_temp_negated_vector(1));
    int_clk_b1_b2 <= Q_temp_negated_vector(1);

    b2 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b1_b2, rst => and_out_reset, set => '0', Q => Q_temp_vector(2), nQ => Q_temp_negated_vector(2));
    int_clk_b2_b3 <= Q_temp_negated_vector(2);

    b3 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b2_b3, rst => and_out_reset, set => '0', Q => Q_temp_vector(3), nQ => Q_temp_negated_vector(3));

    and_vector(0) <= Q_temp_negated_vector(0);
    and_vector(1) <= Q_temp_vector(1);
    and_vector(2) <= Q_temp_negated_vector(2);
    and_vector(3) <= Q_temp_vector(3);
    and_in_values <= and_vector;

    Q_vector <= Q_temp_vector;
    Q_negated_vector <= Q_temp_negated_vector;
END arch;

Testbench code :

library ieee;
use ieee.std_logic_1164.all;

ENTITY tb IS
END tb;

ARCHITECTURE arch OF tb IS
    SIGNAL clk : std_logic := '0';
    SIGNAL Q_vector : std_logic_vector(3 downto 0);
    SIGNAL Q_negated_vector : std_logic_vector(3 downto 0);
    SIGNAL and_in_values : std_logic_vector(3 downto 0);
    SIGNAL and_out_value : std_logic;

    CONSTANT clk_period : time := 1 ns;
BEGIN
    UUT : ENTITY work.brojilo port map(clk => clk, Q_vector => Q_vector, Q_negated_vector => Q_negated_vector, and_in_values => and_in_values, and_out_value => and_out_value);

    clk_process : PROCESS
        VARIABLE counter : integer := 0;
    BEGIN
        if(counter < 31) then
            clk <= '0';
            wait for clk_period/2;
            clk <= '1';
            wait for clk_period/2;
            counter := counter + 1;

        else
            assert false report "End of test";
            wait;
        end if;
    END PROCESS;

END arch;

Waveforms for code above :

Waveforms when rst <= '0' on all JK flip flops :

I have two issues which I can't solve :

1. Before the first clock pulse, there are values in Q and nQ different from 0000. I do not understand where these values stem from.
2. The main problem : it is required to reset the whole counter when B3B2B1B0 is 1010, but the counter never reaches that state. Instead, it resets when the counter is in state 1001, which it shouldn't, given that state in and won't be 1.

Interestingly, when I force 0 to rst input on all JK flip flops, the and starts working correctly, and the and output line fires a 1 on 1010.

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