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arrays - System Verilog 数组缩减陷阱和参数数组

问题描述

我正在尝试在系统 verilog 中学习阵列缩减技术。写在下面的模块：

module main;

localparam [7:0]PARAM_ARR0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
localparam [3:0]PARAM_ARR1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

int s = 0;
logic [7:0]arr0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
logic [3:0]arr1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

initial begin

//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[0])?item:0));
//$display("sum0 = %0d",s);
//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[4])?item:0));
//$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[0])?item:0));
$display("sum0 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[4])?item:0));
$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[7])?item:0));
$display("sum2 = %0d",s);
end

endmodule
  1. 如果我在初始后取消注释前 4 行（二维参数数组的数组缩减），VCS 会抛出如下编译错误。数组方法不适用于参数数组吗？
    Error-[XMRE] Cross-module reference resolution error
    ../../test_param_array_sum.sv, 10
      Error found while trying to resolve cross-module reference.
      token 'sum'.  Originating module 'main'.
      Source info: PARAM_ARR0.sum(item) with (((item.index < int'(4'b1))
      ? item : 0))



    Error-[IND] Identifier not declared
    ../../test_param_array_sum.sv, 10
      Identifier 'item' has not been declared yet. If this error is not expected, 
      please check if you have set `default_nettype to none.
  1. 另一个疑问是，当我在上面给出的 VCS 中模拟代码时，我得到以下结果：
sum0 = 1
sum1 = 4
sum2 = 8

我期望结果分别为 0、4 和 7。因为我试图获取 arr0 中索引分别小于 arr1[0] (1)、arr1[4] (2)、arr1[7] (3) 的所有元素的总和。

谢谢

标签： arrayssystem-verilog

解决方案

这在 Questa 2019.2 中对我有用。您可能需要与您的 EDA AE 讨论问题所在。Serge 对使用动态数组的建议有效：https ://www.edaplayground.com/x/26RL

此外，看起来您的代码正在给出您在 Questa 中预期的结果。

# Loading sv_std.std
# Loading work.main(fast)
# run -all
# sum0 = 0
# sum1 = 4
# sum0 = 0
# sum1 = 4
# sum2 = 7
#  quit -f
# End time: 11:17:11 on May 23,2019, Elapsed time: 0:00:21
# Errors: 0, Warnings: 0

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