for-loop - 是否可以在结构 Verilog 中重复门？

Question

我将在 Verilog 中级联几个缓冲区。我的示例如下，我定义了 16 个缓冲区，它们在结构定义中级联：

BUFX12 BUF01(dummy_wire[1],N62878);
BUFX12 BUF02(dummy_wire[2],dummy_wire[1]);
BUFX12 BUF03(dummy_wire[3],dummy_wire[2]);
BUFX12 BUF04(dummy_wire[4],dummy_wire[3]);
BUFX12 BUF05(dummy_wire[5],dummy_wire[4]);
BUFX12 BUF06(dummy_wire[6],dummy_wire[5]);
BUFX12 BUF07(dummy_wire[7],dummy_wire[6]);
BUFX12 BUF08(dummy_wire[8],dummy_wire[7]);
BUFX12 BUF09(dummy_wire[9],dummy_wire[8]);
BUFX12 BUF10(dummy_wire[10],dummy_wire[9]);
BUFX12 BUF11(dummy_wire[11],dummy_wire[10]);
BUFX12 BUF12(dummy_wire[12],dummy_wire[11]);
BUFX12 BUF13(dummy_wire[13],dummy_wire[12]);
BUFX12 BUF14(dummy_wire[14],dummy_wire[13]);
BUFX12 BUF15(dummy_wire[15],dummy_wire[14]);

由于我要在我的测试设计中更改缓冲区的数量，我正在寻找诸如 for-loop 之类的语法来以自动格式实现以下结构，但我不知道正确的结构。我想知道它是否可能以及正确的语法是什么。此外，最好是实现具有实例名称。

标签： for-loopverilog

Answer 1

使用实例数组：

wire [15:1] other = {dummy_wire[14:1], N62878};
BUFX12 BUF [15:1] (dummy_wire, other);