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vhdl - How can i move next line in VHDL write & writeline function

问题描述

I try to write VHDL simulation result at txt file.

I can write some data.

But i like to stack these data by row order. That is, there is new line between saved data.

I exptected writeline function to move newline. But it isn`t.

TEXT_OUT : process (I_CLK,I_RST)
file    file_RESULTS    : text open write_mode is "output_result.txt";     
variable    v_OLINE        : line;
 begin 
    if (I_RST = '1') then
          null;           
    elsif (rising_edge(I_CLK)) then
       if (I_BRAM_ENA = '1') then
         hwrite(v_OLINE, O_ADDRB, left, 5);      
         writeline(file_RESULTS, v_OLINE);          
             report "Save the output address!";            
       end if;       
    end if;            
 end process;

if O_ADDRB have sequentially 0000, 0001, 0002, as time gone.

Then output_result.txt have data like below

0000

0001

0002

标签： vhdl

解决方案

如果您需要在新行中打印，那么我可能无法帮助您，除非您必须一次性完成所有操作，而不必关闭文件并再次打开（在这种情况下，您可以按照 user1155120 的评论中所述进行操作。但如果只是出于调试目的，则使用此代码在控制台中打印：

library ieee;
use ieee.std_logic_1164.all;

use std.textio.all;
use ieee.std_logic_textio.all;

procedure writeproc(sig: in std_logic_vector; s : string) is
    variable li : line;
    variable str : string(1 to sig'length);
    file f_in : text; -- open read_mode is "output";
    file f_out : text; -- open write_mode is "output";
begin
    file_open(f_out, "output", write_mode);
    write(li, std_logic_vector(sig));
    write(li, lf);  writeline(f_out, li);
    file_close(f_out);
    file_open(f_in, "output", read_mode);
    readline(f_in, li);
    read(li, str);
    file_close(f_in);
    report "read " & s & str;
end procedure writeproc;

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