首页 > 解决方案 > 如何将文本文件的十六进制读取与状态机结合起来

问题描述

我正在尝试实现一个从文本文件读取十六进制的状态机。但是,我对如何进行没有想法。将有四种情况,前两种情况输出一个作为头部的数据序列。即空闲序列和启动序列。第三种情况是我从文本文件数据中读取的实际十六进制数。它读取十六进制数据并逐位发送。最后一种情况发送一个尾序列位。
对于第一个周期,它将发送数据的反转版本。第二个周期将发送实际数据。最后一个周期发送反转版本。在开始新行之前,

编辑:我所说的循环是4个案例的第一个循环

目前,我正在尝试测试它是否可以运行前 3 个周期,然后再继续执行下一行。我还需要弄清楚如何刷新内联数据以读回同一行。我猜inline := new string'(inline.all);

For example my text file has AA 00 on the first line. BB 11 on 2nd line
Using
Idle seq of "010"
start seq of "1110"
tail seq of "11000"
For first cycle at first case it reads in inverted Idle, next case reads inverted start seq then 3rd case inverted of AA 00 and last case inverted of tail seq. 
Then would add a count to sequence and restart with 2nd cycle this time sending actual data. Then 3rd cycle go back to inverted sequence and exit. Before moving on to next line
So.. ( , represent each new case) 
count = 1;
101,0001,0101 1111, 00111. 
Count = 2 condition (send actual data)
010, 1110, 1010 000, 11000
Count = 3
101,0001,0101 1111, 00111. and move on to next line
count = 1 (Reset to 1)
101, 0001, 01000100, 0011
count = 2
010, 1110, 10111011, 11000
count = 3
101, 0001, 01000100, 0011

当我能够查看第一个周期时,我尝试将 case 与我的线程函数一起实现。在我的第二个周期中,我无法读取文本文件,程序停在那里。
看来我不应该再打开文件再次阅读。我猜我需要在案例之前将我的文件打开并读取语句,但是当我这样做时,我无法在我的第一个周期案例中输出任何数据。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.std_logic_textio.all;
LIBRARY STD;
USE STD.textio.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;

entity readtext is
port (  
IN_SRX2_BPSKDAT1: OUT    std_logic;
);
end readtext;

ARCHITECTURE arch_name OF readtext IS
signal clock,endoffile : std_logic := '0';
signal readdatainput : std_logic_vector (7 downto 0);

signal startSeq : std_logic_vector(0 to 3):= "1110"; 
signal tailSeq : std_logic_vector(0 to 4):= "11000"; 
signal idleSeq : std_logic_vector(0 to 2):= "010"; 

signal Bitreading : std_logic;

signal next_dataSendState: std_logic_vector(0 to 1);


BEGIN

clock <= not (clock) after 0.5 ms;   

reading:
process
    file   infile    : text is in  "A.txt";
    variable inline    : line; --line number declaration
    file file_RESULTS : text;
    variable inputdata : std_logic_vector(7 downto 0);
    variable TFSeqCount: integer range 1 to 3;

begin
wait until rising_edge(clock);
    case next_dataSendState is
    when "00"=> 
    for i in idleSeq'range loop
    IN_SRX2_BPSKDAT1 <= not idleSeq(i);
    if (TFSeqCount=2) then
    IN_SRX2_BPSKDAT1 <= idleSeq(i);
    end if;
    wait until rising_edge(clock);
    end loop;           
    next_dataSendState<= "10";

    when "10"=> --staRT
    for i in startSeq'range loop
    IN_SRX2_BPSKDAT1 <= not startSeq(i);
    if (TFSeqCount=2) then
    IN_SRX2_BPSKDAT1 <= startSeq(i);
    end if;
    wait until rising_edge(clock);
    end loop;
    next_dataSendState<= "01";

    when "01"=>  --transmit
    while not endfile(infile) loop  --open file 
    readline(infile, inline);
         while inline.all'length /= 0 loop --check if line have values
         hread (inline, inputdata);
         readdatainput <= inputdata;
         for i in inputdata'range loop
         Bitreading <= inputdata(i);
         IN_SRX2_BPSKDAT1 <= not inputdata(i);
         if (TFSeqCount=2) then
         IN_SRX2_BPSKDAT1 <= inputdata(i);
         end if;
         wait until rising_edge(clock);
         end loop; --end of bitrange
        end loop; --end of line
       end loop; --end of file  

     file_close(infile);  

    next_dataSendState<= "11";

    when "11"=> 
    for i in tailSeq'range loop
    IN_SRX2_BPSKDAT1 <= not tailSeq(i);
    if (TFSeqCount=2) then
    IN_SRX2_BPSKDAT1 <= tailSeq(i);
    end if;
    wait until rising_edge(clock);
    end loop;   
    TFSeqCount:=TFSeqCount+1;           
    next_dataSendState<= "00";
    when others =>
    next_dataSendState<="00";   
    end case;




end process reading;
endoffile <='1';         
END ARCHITECTURE arch_name;


First cycle reads fine. The data isnt reading on 2nd cycle. I am guessing I have to shift the 
while not endfile(infile) loop  --open file 
readline(infile, inline);
while inline.all'length /= 0 loop 
to be above the case somewhere. Additionally I gotta save the line of data as a string to use for 2nd case.

标签: vhdl

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