首页 > 解决方案 > 找到运算符“=”的“0”定义,无法确定“=”的确切重载匹配定义

问题描述

当我想在模拟中检查语法时,我遇到了这个错误。“第 105 行:找到运算符“=”的“0”定义,无法确定“=”的确切重载匹配定义我试图添加库,正如其他人在其他类似线程中所说的那样,但它没有帮助。这是我的代码,我使用的库:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use ieee.std_logic_unsigned.all;
    use IEEE.NUMERIC_STD.ALL;
  -- Uncomment the following library declaration if using
  -- arithmetic functions with Signed or Unsigned values
  --use IEEE.NUMERIC_STD.ALL;

  -- Uncomment the following library declaration if instantiating
  -- any Xilinx primitives in this code.
  --library UNISIM;
  --use UNISIM.VComponents.all;

entity multiwib is

port(trigger : in std_logic;
      reset   : in std_logic;
      CLK     : in std_logic;
      led     : out std_logic
      );

end multiwib;

architecture multiwib_arch of multiwib is
type stany is (stabilny,niestabilny);
 signal stan, stan_nast : stany;
signal licztakty : std_logic_vector(25 downto 0);
signal flaga : std_logic;

begin

reg:process(clk,reset)
begin
    if(reset='1')then
        stan<=stabilny;
    elsif(clk'event and clk='1')then
        stan<=stan_nast;
    end if;
end process reg;


multi:process(clk,trigger)
begin

stan_nast<=stan;

case stan is
      when stabilny=>
             flaga<='0';
             led<='0';
             licztakty<=(others=>'0');

             if(trigger='1')then
             stan<=niestabilny;
             led<='1';
             end if;

        when niestabilny=>

                 if flaga ='1' then

                      stan<=stabilny;
                else 
                      stan<=niestabilny;
                 end if;



 end case;

end process multi;

licznik:process(clk,reset) 开始

    if reset ='1' then
            licztakty<=(others=>'0');
    elsif(clk'event and clk='1') then
            if(stan=niestabilny) then
                licztakty<=licztakty+"01";
                led<='1';
            elsif(stan=niestabilny and licztakty="?10111110101111000010000000?")then
               flaga<='1';
            elsif(stan=stabilny) then
                    licztakty<=(others=>'0');
            end if;

    end if;

end process licznik;

end multiwib_arch;

标签: vectorvhdl

解决方案


你已经写了licztakty="?10111110101111000010000000?"

licztakty 是一个 std_logic_vector 和?不是有效的 std_logic 值。有效的选项是'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'

“?” 使编译尝试将 std_logic_vector 与字符串进行比较,我假设您还没有为比较编写自定义 '=' 函数。


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