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vhdl - 如何在 if 语句中检查输出信号的条件

问题描述

我正在尝试检查输出的条件（可以稍后在代码中设置），但您似乎无法做到这一点。

如何在 if 语句中检查输出信号的条件？

entity turbine_action is
Port (  freq550 : in STD_LOGIC;
        freq650 : in STD_LOGIC;
        freq850 : in STD_LOGIC;
        freq950 : in STD_LOGIC;
        user_ip : in STD_LOGIC;
        mild : out STD_LOGIC;
        aggressive : out STD_LOGIC;
        brake : out STD_LOGIC;
        alarm : out STD_LOGIC;
        clock : in STD_LOGIC);
end turbine_action;

architecture Behavioral of turbine_action is

type state_type is (s0, s1, s2);
signal current_s, next_s : state_type;

begin

process (clock)
begin
    if (rising_edge(clock)) then
        current_s <= next_s;    --change state according to next state logic
    end if;
end process;


process (current_s, freq550, freq650, freq850, freq950, user_ip)
begin
    case current_s is
        when s0 =>
        if (user_ip = '1') then
            if (freq550 = '1') then
                brake <= '1';
                alarm <= '1';
                -- ADD DELAY delay(1000);
            end if;
            if (freq650 = '1') then
                if (mild = '1') then
                    aggressive <= '1';
                end if;
            end if;

end Behavioral;

标签： vhdl

解决方案

Let say you will use this:

alarm : out STD_LOGIC;

You can define it as inout signal:

alarm : inout STD_LOGIC;

Or you can connect it with an signal (assuming you defined a std_logic signal): 

local_signal <= alarm;

Then you can check the condition of local_signal.

Normally output vectors are going to one top vhd file and they can be controlled at that vhd file due to they came as input vector.

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