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timer - 如何在 ARM Cortex-A7 中初始化内核定时器

问题描述

目前，我正在为 Raspberry 2 开发操作系统，这是我获得大学学位的最后一个项目，现在我在创建一个每秒抛出一个中断的简单计时器时遇到了严重的问题，因为提供的文档由ARM 没有说明如何初始化该模块。
我阅读了架构参考手册，它位于ARM 架构/参考手册/ARMv7-AR

有人可以向我解释初始化核心计时器的过程吗？

我将补充到目前为止我尝试过的内容：

在我的 C 文件中

    _local_timer_init();
    // ROUTING IRQ
    *(volatile uint32_t*)CORE0_L_TIMER_INT_CTL = 0x8;

在我的汇编文件中

.globl _local_timer_init
/*
        THIS STEPS APPLIES IN A SYSTEM WHERE THERE IS NOT VIRTUALIZATION SUPPORT
        (I think so)
    1. Look into CNTKCTL register if you need
    2. Look into CNTP_CTL or CNTH_CTL or CNTV_CTL to enable or disable
       the corresponding timer (bit 0)
    3. You have to set the compare value for the corresponding timer
       CNTP_CVAL, CNTH_CVAL, CNTV_CVAL if needed
    4. It should be in boot.S but you have to initialize the counter 
       frequency register, CNTFRQ
    5. Putting the corresponding TVAL register to a right value
    6. Routing the IRQ and enabling IRQ of the corresponding core
*/
_local_timer_init:
    // ENABLING TIMER
    mov r0, #1
    mcr p15, #0, r0, c14, c3, #1 //Write to CNTV_CTL
    // SETTING FREQUENCY TIMER
    //we don't need this right now
    // SETTING TVAL REGISTER (virtual)
    mrc p15, #0, r0, c14, c0, #0 //we obtain CNTFRQ
    mcr p15, #0, r0, c14, c3, #0 //Write to CNTV_TVAL

我还为这样的 IRQ 异常创建了自定义汇编处理程序：也许问题就在这里，我真的不知道这是处理 IRQ 异常的正确方法吗？

irq_s_handler:
    /*Mode: PL1 irq */
    srsda sp!, #0x12 //we stores the spsr and lr at the address contained in sp of the mode irq
    /*
    It is necessary to switch to supervisor mode and store some registers
    into it's stack for having support for nested exceptions
     */
    push {r0-r12}
    bl irq_c_handler
    pop {r0-r12}
    rfeib sp! //we do the inverse operation of srsdb
    subs pc, lr, #4 //we adjust the appropiate value considered

标签： timeroperating-systemarm

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