verilog - 我的 verilog 代码出现此错误,“常量表达式的非法操作”
问题描述
每当我编译此代码时,都会出现以下错误。
module mv2_generate
(
input [127:0] c_array [1:0],
input [127:0] p_array [1:0],
input [127:0] p1_array [1:0],
output reg [15:0] min_mv
);
//genvar index;
integer a, b, index, m;
//genvar m;
// a= (m*7)+m+7;
// b= (m*7)+m;
reg [7:0] read_dataC; //registers for C,P,P'
reg [7:0] read_dataP;
reg [7:0] read_dataP1;
reg [15:0] out_pe0;
reg pe0_en;
pe PE0(.a(read_dataC),.b(read_dataP),.en(pe0_en),.pe_out(out_pe0));
always @*
begin
//generate
for (index=0; index<2; index=index+1)
begin
// assign n=n+1;
// a=7;
// b=0;
for (m=0; m<16; m=m+1)
begin
if(index<2)
begin
if (m>=0)
begin
read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
// read_dataC = c_array [index] [a:b];
// read_dataP = p_array [index] [a:b];
#50;
$display("pe out: %d",out_pe0);
//pe PE0(read_dataC, read_dataP, out_pe0);
end
// a= a+8;
// b= b+8;
end
end
end
end
//endgenerate
//assign min_mv= out_pe0;
endmodule
//
module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out);
//reg [15:0] acc_temp = acc;
always @* begin
//$display("End of Sim: %d", en);
if(en) begin
if (a<b) begin
assign pe_out = b - a;
end
else if (a==b) begin
assign pe_out = 8'd0;
end
else begin
assign pe_out = a - b;
end
//acc_temp = acc_temp + pe_out;
//acc = acc_temp;
//$display("End of Sim: %d", acc);
end
else begin
pe_out = 8'd0;
end
end
endmodule
错误
ncverilog(64): 15.20-s029: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
file: mv2test.v
read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,38|42): Illegal operand for constant expression [4(IEEE)].
read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,38|47): Illegal operand for constant expression [4(IEEE)].
read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,38|52): Illegal operand for constant expression [4(IEEE)].
read_dataC = c_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,38|57): Illegal operand for constant expression [4(IEEE)].
read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,39|42): Illegal operand for constant expression [4(IEEE)].
read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,39|47): Illegal operand for constant expression [4(IEEE)].
read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,39|52): Illegal operand for constant expression [4(IEEE)].
read_dataP = p_array [index] [(m*7)+m+7:(m*7)+m];
|
ncvlog: *E,NOTPAR (mv2test.v,39|57): Illegal operand for constant expression [4(IEEE)].
module worklib.mv2_generate:v
errors: 8, warnings: 0
module pe(input [7:0] a, input [7:0] b, input en, output reg [7:0] pe_out);
|
ncvlog: *W,RECOME (mv2test.v,83|8): recompiling design unit worklib.pe:v.
First compiled from line 59 of mv2test.v.
ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
解决方案
这在 Verilog(和 SystemVerilog)中是非法的:
c_array [index] [(m*7)+m+7:(m*7)+m];
:
具体来说,您不能在part select的右侧有一个变量。相反,您需要编写以下任一内容:
c_array [index] [(m*7)+m+7 -: 8];
或这个:
c_array [index] [(m*7)+m +: 8];
-:
和运算符左侧的值+:
是起始索引。右边的数字是宽度。这必须是恒定的。因此,你的错误。操作员从-:
起始索引开始倒计时;操作员+:
数起来。原始数组声明的方向无关紧要:无论数组的方向如何,您都可以使用任一运算符。
推荐阅读
- r - 在 R 中使用不同级别参数计数
- python-3.x - python matplotlib底图系统崩溃问题中的多图单色条
- linux - 复制到 SD 卡更改执行权限 (Linux)
- c# - ServiceStack Proxy 功能代码优化
- r - 使用 rename_all 从列名中删除数字
- javascript - 将字符串转换为日期时间并使用 js 或应用程序脚本在谷歌表格中添加 5:30 小时
- typescript - 如何定义一种类型,省略工会中的一个共享道具,但将其余道具与工会成员的私有道具一起包括在内?
- c# - SqlCommand 里面的 SqlDataReader 里面的 SqlCommand
- android - Android 10 上的自定义通知中没有展开按钮
- python - 在python中拟合卷积