vhdl - 未定义符号错误，但符号似乎在代码 VHDL 中定义

问题描述

所以，我不断收到这些错误，我不知道如何解决它们，因为我在代码中定义了组件。这些是错误：

错误：HDLParsers:3312 -“D:/licenta/multyv3/multy.vhd”第 123 行。未定义符号“D”。错误：HDLParsers：1209 -“D:/licenta/multyv3/multy.vhd”第 123 行。D：未定义符号（此块中的最后报告）错误：HDLParsers：3312 -“D:/licenta/multyv3/multy.vhd”第 124 行。未定义的符号“Q”。错误：HDLParsers:1209 -“D:/licenta/multyv3/multy.vhd”第 124 行。问：未定义符号（此块中的最后报告）

错误在 cell_4 中

entity multy is 

 port (
     x: in  std_logic_vector (3 downto 0);
     y: in  std_logic_vector (3 downto 0);
     p: out std_logic_vector (7 downto 0);
       clk: in std_logic
 );
end entity multy;

architecture rtl of multy is
 component Ripple_Adder
     port ( 
         A:      in  std_logic_vector (3 downto 0);
         B:      in  std_logic_vector (3 downto 0);
         Cin:    in  std_logic;
         S:      out std_logic_vector (3 downto 0);
        Cout:    out std_logic
     );
 end component;

 component FlipFlopPack

 generic(
N : integer := 4
 );

port(
   Q : out std_logic_vector (N-1 downto 0);    
   Clk : in std_logic;   
   D : in  std_logic_vector (N-1 downto 0)    
);
     end component;

-- AND Product terms:
 signal G0, G1, G2:  std_logic_vector (3 downto 0);
-- B Inputs (B0 has three bits of AND product)
 signal B0, B1, B2:  std_logic_vector (3 downto 0);
-- D flip flop signals (Qyout)
 signal I: std_logic_vector (3 downto 0);
-- D flip flop signal (Qxout)
  signal O: std_logic_vector (3 downto 0);
-- d flip flop signal for S
 signal S1, S2, S3: std_logic_vector (3 downto 0);
--  signal for p
 signal P1: std_logic_vector (3 downto 0);
begin

 -- y(1) thru y (3) AND products, assigned aggregates:
 G0 <= (O(3) and I(1), O(2) and I(1), O(1) and I(1), O(0) and I(1));
 G1 <= (O(3) and I(2), O(2) and I(2), O(1) and I(2), O(0) and I(2));
 G2 <= (O(3) and I(3), O(2) and I(3), O(1) and I(3), O(0) and I(3));
 -- y(0) AND products (and y0(3) '0'):
 B0 <=  ('0',          O(3) and I(0), O(2) and I(0), O(1) and I(0));

-- named association:
cell_1: 
 Ripple_Adder 
     port map (
         a => G0,
         b => B0,
         cin => '0',
         cout => S1(3), -- named association can be in any order 
         S(3) => S1(2), -- individual elements of S, all are associated
         S(2) => S1(1), -- all formal members must be provide contiguously
         S(1) => S1(0),
         S(0) => P1(1)
     );

cell_2: 
 Ripple_Adder 
     port map (
         a => G1,
         b => B1,
         cin => '0',
         cout => S2(3),
             S(3) => S2(2),
         S(2) => S2(1),
         S(1) => S2(0),
         S(0) => P1(2)
     );

cell_3: 
 Ripple_Adder 
     port map (
         a => G2,
         b => B2,
         cin => '0',
         cout => S3(3),
             S(3) => S3(2),
         S(2) => S3(1),
         S(1) => S3(0),
         S(0) => P1(3)
     );

cell_4:
     FlipFlopPack
         port map (
             x => D,
             O => Q,
             clk => clk
         );

cell_5:
     FlipFlopPack
         port map (
             y => D,
             I => Q,
             clk => clk
         );

cell_6:
     FlipFlopPack
         port map (
             S1 => D,
             B1 => Q,
             clk => clk
         );

cell_7:
     FlipFlopPack
         port map (
             S2 => D,
             B2 => Q,
             clk => clk
         );

cell_8:
     FlipFlopPack
         port map (
             S3 => D,
             p(7 downto 4) => Q,
             clk => clk
         );

cell_9:
     FlipFlopPack
         port map (
             P(3 downto 0) => D,
             p(3 downto 0) => Q,
             clk => clk
         );




P1(0) <= O(0) and I(0); 
end architecture rtl;

标签： vhdl

vhdl - 未定义符号错误，但符号似乎在代码 VHDL 中定义

问题描述

解决方案

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