vhdl - 行为模拟有效，但合成后模拟无效

Question

我的组件在行为模拟中运行良好，但是当我尝试后合成模拟时它根本不起作用。我认为主要问题是在合成过程中没有连接端口。显然，这个端口必须连接！

综合中的其他警告是：“推断锁存器”、“信号不在敏感度列表中”

这是架构和信号声明。我不确定问题是在这里还是其他地方。

    PORT (      
        -- inputs
        i_clk       : IN std_logic;                         
        i_start     : IN std_logic;                         
        i_rst       : IN std_logic;                         
        i_data      : IN std_logic_vector(7 DOWNTO 0);      
        --outputs
        o_address   : OUT std_logic_vector(15 DOWNTO 0);    
        o_done      : OUT std_logic;                        
        o_en        : OUT std_logic;                        
        o_we        : OUT std_logic;                        
        o_data      : OUT std_logic_vector (7 DOWNTO 0)     
    );
END myEntity;   


ARCHITECTURE beh OF myEntity IS 

    --*********** CONSTANT ****************
    CONSTANT Nwz    : integer := 8; 
    CONSTANT Dwz    : integer := 4;     

    --*********** signals ****************  
    SIGNAL timer : natural := 0; -- timer dei clock per lettura RAM

    -- component OUTPUT signals
    SIGNAL my_o_done    : std_logic := '0';                                     

    -- component OUTPUT signals for RAM
    SIGNAL my_o_address : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z');     
    SIGNAL my_o_we      : std_logic := 'Z';                                     
    -- RAM signals
    SIGNAL my_mem_do   : std_logic_vector (7 DOWNTO 0):= (OTHERS => 'Z');       
    -- FSM signals
    SIGNAL WZ_NUM       : integer range 0 TO 7 := 0;                            
    SIGNAL WZ_OFFSET    : std_logic_vector (3 DOWNTO 0) := (others => '0');     
    SIGNAL ADDR         : std_logic_vector (6 DOWNTO 0) := (others => '0');     
    SIGNAL WZSTART      : std_logic_vector (6 DOWNTO 0) := (others => '0');     
    SIGNAL WZEND        : std_logic_vector (6 DOWNTO 0) := (others => '0');     
    -- FSM states
    SIGNAL PS   : FSM_state := LCK;     -- FSM Present State
    SIGNAL NS   : FSM_state;            -- FSM Next State   

    -- controller SEC signals
    SIGNAL SEC_start :  std_logic_vector (1 TO 4) := "Z000";
    SIGNAL SEC_end   :  std_logic_vector (1 TO 4) := (OTHERS => '0');

    -- secCOMP signals
    SIGNAL cmp_en   :   std_logic := 'Z'; 
    SIGNAL cmp_r1   :   std_logic_vector(6 DOWNTO 0);
    SIGNAL cmp_r2   :   std_logic_vector(6 DOWNTO 0);    
    SIGNAL cmp_done :   std_logic := '0';
    SIGNAL cmp_cc   :   std_logic_vector(1 TO 2);
    -- secADDER signals
    SIGNAL add_en   :   std_logic := 'Z';       
    SIGNAL add_r1   :   std_logic_vector(6 DOWNTO 0);
    SIGNAL add_r2   :   std_logic_vector(6 DOWNTO 0);    
    SIGNAL add_done :   std_logic := '0';
    SIGNAL add_sum  :   std_logic_vector(6 DOWNTO 0) := (OTHERS => 'Z');

    -- secONEHOT signals
    SIGNAL one_en   :   std_logic := 'Z';   
    SIGNAL one_inc  :   std_logic := '0';   
    SIGNAL one_di   :   std_logic_vector(3 DOWNTO 0);
    SIGNAL one_done :   std_logic;
    SIGNAL one_do   :   std_logic_vector(3 DOWNTO 0);```

标签： vhdlvivado