vhdl - 使用控制单元和数据流的 VHDL log2

Question

我需要以数据流和控制单元的形式实现一个数字电路，以计算正数 N 的以 2 为底的对数的整个部分，表示为一个无符号的 8 位整数。为此，电路将 N 反复向右移动，直到获得值 0（零）。计算的结果是从 1 中减去的位移总数。

例子：对于log2(18) = log2(00010010)，计算顺序如下： 00010010 => 00001001 => 00000100 => 00000010 => 00000001 => 00000000

进行 5 次位移时，log2 (18) = 5 - 1 = 4。

事实上，log2 (18) = 4.169925，所以对整个部分回答“4”是正确的。当输入 N 为 0（零），对数值应为 –∞ 时，给出答案“-1”（二进制 1111）

我刚开始用 VHDL 编码，所以我认为我的代码很糟糕我已经这样做了：但它根本不起作用，我有点不知道还能做什么

   library IEEE;

entity log2 is 
    port ( 
        clock, reset : in bit;
        start        : in bit;
        ready        : out bit;
        N            : in bit_vector(7 downto 0);
        logval       : out bit_vector (3 downto 0)
        );
end entity log2;

architecture log2_arch of log2 is

        component log2_UC 
            port (
                reset, start : in bit;
                clock: in bit;
                ready : out bit;    
                N : in bit_vector(7 downto 0);
                logval: in bit_vector(3 downto 0)
            );
        end component;
        
        component log2_FD
            port (
                clock : in  bit; 
                N : in bit_vector(7 downto 0)
            );
        end component;
        
        signal entry: bit_vector(7 downto 0);
        signal result: bit_vector(3 downto 0);  
    
begin
    
    UC: log2_UC port map (
            reset => reset,
            start => start,
            clock => clock,
            ready => ready,
            N => entry,
            logval => result
    );
    
    FD: log2_FD port map (
        clock => clock,
        N => entry
    );
end architecture;
        
    
entity log2_UC is
    port (
        reset, start : in bit;
        clock: in bit;
        ready : out bit;    
        N : in bit_vector(7 downto 0);
        logval: in bit_vector(3 downto 0)
    );
end entity log2_UC;

architecture log2_UC_arch of log2_UC is
  type state_t is (wait0, x1, x2, fins);
  signal next_state, current_state: state_t;
begin
    process(clock, reset)
    begin 
        if reset='1' then
          current_state <= wait0;

        elsif (clock'event and clock='1') then
          current_state <= next_state;
        end if;
      end process;
    
    next_state <=
    wait0 when (current_state = wait0) and (start = '0') else
    x1    when (current_state = wait0) and (start = '1') else
    x2    when (current_state = x1)    and (logval = "1111") 
    ;
      
    logval  <= "1111" when current_state=x1 else '0';



    Ready <= '1' when current_state=fins else '0';
end log2_UC_arch;


entity log2_FD is 
  port (
    clock : in  bit; 
    N : in bit_vector(7 downto 0)
    ); 
end log2_FD;
 
architecture archi of log2_FD is 
  signal reg: bit_vector(7 downto 0); 
  signal logval:  bit_vector(3 downto 0);
  signal ready:  bit;
  
  begin 
    process (clock) 
      begin 
        for i in 0 to 7 loop 
            reg(i) <= N(i); 

        logval <= "1111"; 
        ready <= '0';
        
        for i in 0 to 7 loop
            nor reg(i) <= '0';
        end loop;

        if (clock'event and clock='1') then 
          for i in 7 downto 0 loop 
            reg(i) <= reg(i-1); 
            logval <= logval + 1;
          end loop; 
        end if; 
    end process;
end archi; 

标签： vhdl