vhdl - VHDL代码和测试台有什么错误吗？

Question

我一直在 Quartus 2 中尝试时钟触发器，但收到以下错误

错误 (10533)：T17_ClockedProcessTb.vhd(42) 处的 VHDL 等待语句错误：等待语句必须包含带有 UNTIL 关键字的条件子句

我为触发器创建了以下代码

library ieee;
use ieee.std_logic_1164.all;

entity T17_FlipFlop is
port (
      clk: in std_logic;
      nRst: in std_logic;
        Input: in std_logic;
        Output: out std_logic);
        end entity;
        
architecture rtl of T17_FlipFlop is
begin 
     process(Clk) is
      begin 
           if rising_edge(Clk) then
                 if nRst= '0' then
                     Output<= '0';
                  else
                     Output<= Input;
                  end if;
             end if;
     end process;
end architecture; 

我也为此创建了一个测试平台

library ieee;
use ieee.std_logic_1164.all;

entity T17_ClockedProcessTb is
end entity;

architecture sim of T17_ClockedProcessTb is
    constant ClockFrequency : integer := 100e6; --100 MHz
     constant ClockPeriod : time := 1000 ms; 
     
     signal ClK : std_logic := '1';
     signal nRst: std_logic := '0';
     signal Input: std_logic:= '0';
     signal Output: std_logic;

    begin
        --The Device Under Test (DUT)
         i_FlipFlop : entity work.T17_FlipFlop(rtl)
         port map(
                  ClK => Clk,
                     nRst => nRst,
                     Input => Input,
                     Output => Output);
         --Process for generating clock 
         Clk <= not Clk after ClockPeriod /2 ;
         --Testbench sequence
         process is
         begin 
             --The the DUT out of reset 
              nRst<= '1';
              
              --wait for 20 ns;
              Input<= '1' after 20 ns;
              --wait for 22 ns;
              Input<= '0' after 22 ns;
              --wait for 6  ns;
              Input<= '1' after 6 ns;
              --wait for 20 ns;
              
              --Reset the DUT
              nRst<= '0' after 20 ns;
              wait;
              
         end process;
end architecture;                           
      

我编译了第一个代码，然后编译了第二个代码，但我在做同样的事情时出错了？

我能做些什么来删除它们？

标签： vhdlquartus