vhdl - VHDL 神秘红波

Question

我正在构建一个“包裹分类器”，它基本上需要一个重量，并根据该重量将它添加到一个特定的组中，并使用一个简单的计数器跟踪每个组中有多少重量（又名包裹）。但是，在运行我的测试台时，我遇到了不应该存在的奇怪的红波：

现在我已经读到这些可能主要是由于从两个不同的位置为相同的信号分配了一个值，但是我一直未能找到罪魁祸首并且截止日期即将到来。这是我的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity packageSorter is
    port (clk,reset: in std_logic;
        weight: in std_logic_vector (11 downto 0);
        grp1: out std_logic_vector(7 downto 0);
        grp2: out std_logic_vector(7 downto 0);
        grp3: out std_logic_vector(7 downto 0);
        grp4: out std_logic_vector(7 downto 0);
        grp5: out std_logic_vector(7 downto 0);
        grp6: out std_logic_vector(7 downto 0);
        
        currentGrp: out std_logic_vector(2 downto 0))   ;


end packageSorter;


architecture beh of packageSorter is

    signal count1 : integer range 0 to 256;
    signal count2 : integer range 0 to 256;
    signal count3 : integer range 0 to 256;
    signal count4 : integer range 0 to 256;
    signal count5 : integer range 0 to 256;
        signal count6 : integer range 0 to 256;
    signal lastWeight : std_logic_vector (11 downto 0);
    signal currentWeight : std_logic_vector (11 downto 0);
    begin
    process(clk)
    begin
    if rising_edge(clk) then
    if(reset = '1') then
        count1 <= 0;
        count2 <= 0;
        count3 <= 0;
        count4 <= 0;
        count5 <= 0;
            count6 <= 0;
        lastWeight <= "000000000000";
        currentWeight <= Weight; -- intermediate signal equal to input

    end if;

  if to_integer(unsigned(lastWeight)) = 0 then --IF LAST WEIGHT WAS 0

            if to_integer(unsigned(weight)) = 0 then
                    currentGrp <= std_logic_vector(to_unsigned(0,3));
            elsif to_integer(unsigned(weight)) >= 1 and to_integer(unsigned(weight)) <= 200 then --group 1
                    count1 <= (count1 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(1,3));
                    lastWeight <= weight;
            elsif to_integer(unsigned(weight)) >= 201 and to_integer(unsigned(weight)) <= 500 then --group 2
                    count2 <= (count2 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(2,3));
                    lastWeight <= weight;
            elsif to_integer(unsigned(weight)) >= 501 and to_integer(unsigned(weight)) <= 800 then --group 3
                    count3 <= (count3 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(3,3));
                    lastWeight <= weight;
            elsif to_integer(unsigned(weight)) >= 801 and to_integer(unsigned(weight)) <= 1000 then --group 4
                    count4 <= (count4 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(4,3));
                    lastWeight <= weight;
            elsif to_integer(unsigned(weight)) >= 1001 and to_integer(unsigned(weight)) <= 2000 then --group 5
                    count5 <= (count5 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(5,3));
                    lastWeight <= weight;
            elsif to_integer(unsigned(weight)) >= 2000 then --group 6
                    count6 <= (count6 + 1);
                    currentGrp <= std_logic_vector(to_unsigned(6,3));
                    lastWeight <= weight;
            end if;
        
 elsif to_integer(unsigned(lastWeight)) /= 0 then

            lastWeight <= std_logic_vector(unsigned(Weight) + unsigned(lastWeight));
            currentWeight <= lastWeight; --currentWeight is whatever the input weight is

            if to_integer(unsigned(currentWeight)) = 0 then
                    currentGrp <= std_logic_vector(to_unsigned(0,3));
                    lastWeight <= "000000000000";
            elsif to_integer(unsigned(currentWeight)) >= 1 and to_integer(unsigned(currentWeight)) <= 200 then --group 1
                    currentGrp <= std_logic_vector(to_unsigned(1,3));
            elsif to_integer(unsigned(currentWeight)) >= 201 and to_integer(unsigned(currentWeight)) <=500 then --group 2
                    currentGrp <= std_logic_vector(to_unsigned(2,3));
            elsif to_integer(unsigned(currentWeight)) >= 501 and to_integer(unsigned(currentWeight)) <= 800 then --group 3
                    currentGrp <= std_logic_vector(to_unsigned(3,3));
            elsif to_integer(unsigned(currentWeight)) >= 801 and to_integer(unsigned(currentWeight)) <= 1000 then --group 4
                    currentGrp <= std_logic_vector(to_unsigned(4,3));
            elsif to_integer(unsigned(currentWeight)) >= 1001 and to_integer(unsigned(currentWeight)) <= 2000 then --group 5
                    currentGrp <= std_logic_vector(to_unsigned(5,3));
            elsif to_integer(unsigned(currentWeight)) >= 2001 then --group 6
                    currentGrp <= std_logic_vector(to_unsigned(6,3));
            end if;
            
        end if;

    end if;


    end process;
    grp1 <= std_logic_vector(to_unsigned(count1,8));
    grp2 <= std_logic_vector(to_unsigned(count2,8));
    grp3 <= std_logic_vector(to_unsigned(count3,8));
    grp4 <= std_logic_vector(to_unsigned(count4,8));
    grp5 <= std_logic_vector(to_unsigned(count5,8));
    grp6 <= std_logic_vector(to_unsigned(count6,8));

end beh;    

绝对值得注意的是，即使没有任何分配，即使时钟信号（在上升沿触发计数器）也会变红并损坏，如第一波所示。我已经包括了我的测试台以及我不确定问题是否可能源于那里，但我怀疑是这种情况

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity packageSorter_TB is
end packageSorter_TB;

architecture tb of packageSorter_TB is
    component packageSorter
    port (clk,reset: in std_logic;
          weight: in std_logic_vector (11 downto 0);
          grp1: out std_logic_vector(7 downto 0);
          grp2: out std_logic_vector(7 downto 0);
          grp3: out std_logic_vector(7 downto 0);
          grp4: out std_logic_vector(7 downto 0);
          grp5: out std_logic_vector(7 downto 0);
          grp6: out std_logic_vector(7 downto 0);
          
          currentGrp: out std_logic_vector(2 downto 0));
    end component;

    signal TB_clk: std_logic := '0';
    signal TB_reset :  std_logic := '0';
    signal TB_weight : std_logic_vector (11 downto 0) := "000000000000";
    signal TB_grp1, TB_grp2, TB_grp3, TB_grp4, TB_grp5, TB_grp6 : std_logic_vector(7 downto 0) := "00000000";
    signal TB_currentGrp: std_logic_vector(2 downto 0) := "000";

    begin
      UUT : packageSorter port map ( clk => TB_clk, reset => TB_reset, weight => TB_weight, grp1 => TB_grp1, grp2 => TB_grp2, grp3 => TB_grp3,
                                     grp4 => TB_grp4, grp5 => TB_grp5, grp6 => TB_grp6, currentGrp => TB_currentGrp);
    TB_clk <= '0' after 10 ns;
      TB_clk <= '1' after 20 ns;
      TB_weight <= "000011111010" after 30 ns; --250
      TB_clk <= '0' after 40 ns, '1' after 50 ns;
      TB_weight <= "000000000000" after 60 ns; 
      TB_clk <= '0' after 70 ns, '1' after 80 ns;
      TB_weight <= "000111111010" after 90 ns; --506
    
 --     TB_clk <= '0' after 35ns;
 --     TB_clk <= '1' after 40ns;
 --     TB_weight <= "000100000000" after 40ns; 
 --     TB_clk <= '0' after 45ns;
 --     TB_clk <= '1' after 50ns;
 --     TB_weight <= "000000000000" after 50ns; 
 --     TB_clk <= '0' after 55ns;
 --     TB_clk <= '1' after 60ns;
 --     TB_weight <= "000111110100" after 60ns;
 --     TB_clk <= '0' after 65ns;
 --     TB_reset <= '1' after 70ns;
 --     TB_clk <= '1' after 75ns;
 --     TB_weight <= "000000000001" after 75ns;
      
          end tb;

我感谢任何甚至阅读这些代码块的人。谢谢。

标签： vhdllogical-operators