vhdl - 尝试编译 VHDL 代码时，“架构”内发生错误

Question

我正在尝试为具有 3 个状态的状态机编写代码（+第四个初始状态，在它离开后到达，即在第二个时钟脉冲中）。状态机的输出连接到三个 LED，如果方向为真，则 LED 应按此顺序点亮 100>010>001（循环），如果方向为，则 LED 应按此顺序点亮 001>010> 100。当机器第一次启动时，哪个 LED 亮起并不重要，在我的情况下，我选择无 (000)。问题是，当我尝试编译代码时，我得到以下相当神秘的（至少对于像我这样的初学者）错误消息：

 Error occurred within 'ARCHITECTURE' at line 14, column 28 in IC.vhd.

代码中标记了第 86 行。这是完整的输出：

Compiling 'IC.vhd' in 'C:\VHDL\MyProjects'.
VHDL parser (vhdlfe V6.3 IR 35)
Library 'work' => directory 'lc22v10'
Linking 'C:\Program Files\Cypress\Warp\bin\std.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\Warp\lib\common\work\cypress.vif'.
Library 'ieee' => directory 'C:\Program Files\Cypress\Warp\lib\ieee\work'
Linking 'C:\Program Files\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
IC.vhd (line 86, col 8):  (E0) syntax error
Error occurred within 'ARCHITECTURE' at line 14, column 28 in IC.vhd.

这是我的代码：

library IEEE;

use IEEE.std_logic_1164.all;

entity ic is
    port(clk, direction:in std_logic; output:out std_logic_vector(2 dowton 0));
end ic;

architecture Moore of ic is
    type latches_state is (st0,st1,st2,st3);
    signal state:latches_state;
        begin
            next_state:process(clk)
                begin
                    if rising_edge(clk) then
                       case state is
                           when st0=>
                              if direction='1' then
                                  state<=st1;
                              else
                                  state<=st3;
                            end if;

                        when st1=>
                          if direction='1' then
                              state<=st2;
                        else
                             state<=st3;
                        end if;

                    when st2=>
                          if direction='1' then
                              state<=st3;
                          else
                              state<=st1;
                         end if;

                    when st3=>
                          if direction='1' then
                              state<=st1;
                          else
                              state<=st2;
                          end if;
            end case;
        end if;
    end process next_state;

    output-proc:process(state)//This is line 86 (This comment does not exist in the original code I am trying to compile)
    begin
        if state=st0 then output<="000";
        elsif state=st1 then output<="001";
        elsif state=st2 then output<="010";
        elsif state=st3 then output<="100";
        end if;
    end process output-pro;
end Moore;

标签： vhdl