vhdl - “索引名称不是 std_logic_vector”

Question

我试图在我的代码中使用“端口映射”，但我不知道如何修复错误。它说两个端口映射的“索引名称不是std_logic_vector”。我必须实现下面的电路。

我做了计数器和 MPG 并将它们添加为组件，它们分别工作。我将留下电路的代码。它说这是“端口地图”的问题。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_env is
    Port ( clk : in STD_LOGIC;
           btn : in STD_LOGIC_VECTOR (15 downto 0);
           sw : in STD_LOGIC_VECTOR (15 downto 0);
           led : out STD_LOGIC_VECTOR (15 downto 0));
end test_env;

architecture Behavioral of test_env is
component MPG
    Port(clk : in STD_LOGIC;
         btn : in STD_LOGIC_VECTOR (15 downto 0);
         enable : out STD_LOGIC);
end component;

component counter
    Port ( clk : in STD_LOGIC;
           btn : in STD_LOGIC_VECTOR (15 downto 0);
           sw : in STD_LOGIC_VECTOR (15 downto 0);
           led: out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal en: STD_LOGIC;
signal s: STD_LOGIC_VECTOR(2 downto 0);
signal dcd: STD_LOGIC_VECTOR (7 downto 0);
begin
    --led<=sw;
    --an<=btn(3 downto 0);
    --cat<=(others=>'0');
    process(s)
    begin
        case s is 
            when "000" => dcd<="00000001";
            when "001" => dcd<="00000010";
            when "010" => dcd<="00000100";
            when "011" => dcd<="00001000";
            when "100" => dcd<="00010000";
            when "101" => dcd<="00100000";
            when "110" => dcd<="01000000";
            when others => dcd<="10000000";
        end case;
    end process;
    
    monopulse: MPG port map(clk, btn, en);
   count: counter port map(clk, btn, sw(0), s);
    led(7 downto 0)<= dcd;  
end Behavioral;

我也会留下组件的代码

计数器（16 位）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
   Port ( clk : in STD_LOGIC;
           btn : in STD_LOGIC_VECTOR (15 downto 0);
           sw : in STD_LOGIC_VECTOR (15 downto 0);
           led: out STD_LOGIC_VECTOR (15 downto 0));
end counter;

architecture Behavioral of counter is
signal Q: STD_LOGIC_VECTOR (15 downto 0);
begin
    process(btn)
    begin
       if rising_edge(clk) then
          if(btn(0)='1') then 
            if(sw(0)='1') then
                Q<= Q + "0000000000000001";
            else Q<=Q - "0000000000000001";
            end if;
           end if;
        end if;
     end process;
     led<=Q;
end Behavioral;

手推车

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MPG is
    Port(clk : in STD_LOGIC;
         btn : in STD_LOGIC_VECTOR (15 downto 0);
         enable : out STD_LOGIC);
end MPG;

architecture Behavioral of MPG is
signal count : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal Q1 : STD_LOGIC;
signal Q2 : STD_LOGIC;
signal Q3 : STD_LOGIC;
begin
    enable<=Q2 and (not(Q3));
    process(btn)
        begin
        if rising_edge(clk) then
            count<=count + "0000000000000001";
        end if;
        end process;
    
    process(btn)
    begin
        if rising_edge(clk) then
            if count(15 downto 0)= "1111111111111111" then
                Q1<=btn(1);
            end if;
        end if;
    end process;
    
    process(btn)
    begin
        if rising_edge(clk) then
            Q2<=Q1;
            Q3<=Q2;
        end if;
    end process;
end Behavioral;

如果有人可以帮助我，非常感谢！

标签： vhdlxilinxvivado