verilog - 如何在systemVerilog中返回一个数组

问题描述

我在从 systemVerilog 中的函数返回数组时遇到一些问题。但是，我一直遇到语法错误。我不确定在这里引用数组是否有效，因为我需要将 args 发送到我的函数。

代码：

module VGA_Setup 
(
        input wire clk, reset,
        output wire hsync, vsync,
        output wire [3:0] r, g, b
        
    );
    
    // constant declarations for VGA sync parameters
    localparam H_DISPLAY       = 640; // horizontal display area
    localparam H_L_BORDER      =  48; // horizontal left border
    localparam H_R_BORDER      =  16; // horizontal right border
    localparam H_RETRACE       =  96; // horizontal retrace
    localparam H_MAX           = H_DISPLAY + H_L_BORDER + H_R_BORDER + H_RETRACE - 1;
    localparam START_H_RETRACE = H_DISPLAY + H_R_BORDER;
    localparam END_H_RETRACE   = H_DISPLAY + H_R_BORDER + H_RETRACE - 1;
    
    localparam V_DISPLAY       = 480; // vertical display area
    localparam V_T_BORDER      =  10; // vertical top border
    localparam V_B_BORDER      =  33; // vertical bottom border
    localparam V_RETRACE       =   2; // vertical retrace
    localparam V_MAX           = V_DISPLAY + V_T_BORDER + V_B_BORDER + V_RETRACE - 1;
   localparam START_V_RETRACE = V_DISPLAY + V_B_BORDER;
    localparam END_V_RETRACE   = V_DISPLAY + V_B_BORDER + V_RETRACE - 1;
    int sq_pix = 80;
    
    wire video_on, p_tick;
    int colours [3];

    
    reg [3:0] red_reg, green_reg, blue_reg;
    reg [11:0] rbg;
    
    // mod-2 counter to generate 25 MHz pixel tick
    reg pixel_reg = 0;
    wire pixel_next;
    wire    pixel_tick;
    
    always @(posedge clk)
        pixel_reg <= pixel_next;
    
    assign pixel_next = ~pixel_reg; // next state is complement of current
    
    assign pixel_tick = (pixel_reg == 0); // assert tick half of the time
    
    // registers to keep track of current pixel location
    reg [9:0] h_count_reg, h_count_next, v_count_reg, v_count_next;
    
    // register to keep track of vsync and hsync signal states
    reg vsync_reg, hsync_reg;
    wire vsync_next, hsync_next;
 
    // infer registers
    always @(posedge clk)
        if(~reset)
            begin
                    v_count_reg <= 0;
                    h_count_reg <= 0;
                    vsync_reg   <= 0;
                    hsync_reg   <= 0;
                end
        else
            begin
                    v_count_reg <= v_count_next;
                    h_count_reg <= h_count_next;
                    vsync_reg   <= vsync_next;
                    hsync_reg   <= hsync_next;
                end
            
    // next-state logic of horizontal vertical sync counters
    always @*
        begin
        h_count_next = pixel_tick ? 
                       h_count_reg == H_MAX ? 0 : h_count_reg + 1
                   : h_count_reg;
        
        v_count_next = pixel_tick && h_count_reg == H_MAX ? 
                       (v_count_reg == V_MAX ? 0 : v_count_reg + 1) 
                   : v_count_reg;
                     
                     
            
                     
                     
                     
        end 
                
            
        // hsync and vsync are active low signals
        // hsync signal asserted during horizontal retrace
        assign hsync_next = h_count_reg >= START_H_RETRACE 
                            && h_count_reg <= END_H_RETRACE;
   
        // vsync signal asserted during vertical retrace
        assign vsync_next = v_count_reg >= START_V_RETRACE 
                            && v_count_reg <= END_V_RETRACE;

        // video only on when pixels are in both horizontal and vertical display region
        assign video_on = (h_count_reg < H_DISPLAY) 
                           && (v_count_reg < V_DISPLAY);

        // output signals
        assign hsync  = hsync_reg;
        assign vsync  = vsync_reg;
        assign p_tick = pixel_tick; 
          
          
         colours = Letter_J(h_count_reg,v_count_reg);
          
          
// output
        assign r = (video_on) ? colours[0] : 4'b0;
          assign g = (video_on) ? colours[1] : 4'b0;
          assign b = (video_on) ? colours[2] : 4'b0;
          

                    
endmodule


function int[] Letter_J (int h_count_reg, int v_count_reg);

int colours_red = 0;
int colours_green = 0;
int colours_blue = 0;
int colours [3];

if ((h_count_reg > 160) && (h_count_reg < 400)) begin
    if ((h_count_reg > 240) && (h_count_reg < 320)) begin
        if ((v_count_reg > 80) && (v_count_reg < 240)) begin
            colours_red = 4'b1111;
            colours_green = 4'b1111;
            colours_blue = 4'b1111;
        end
    
    end

end else begin
            colours_red = 4'b0000;
            colours_green = 4'b0000;
            colours_blue = 4'b0000;

end

colours [0] = colours_red;
colours [1] = colours_green;
colours [2] = colours_blue;
return colours;
endfunction

错误：

错误 (10170)：VGA_Setup.sv(108) 附近文本处的 Verilog HDL 语法错误：“=”；期待“。”或“（”。检查并修复紧接在指定关键字之前或处出现的任何语法错误...

谢谢您的帮助。

乔

标签： verilogsystem-verilogfpga

verilog - 如何在systemVerilog中返回一个数组

问题描述

解决方案

推荐阅读