vhdl - 7 4 xilinx 中的汉明解码器（显示警告“温度应在进程的敏感度列表中”）

Question

这就是我正在实施的。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sammy_2018314405 is
    Port ( codeword : in  STD_LOGIC_VECTOR (6 downto 0);
           syndrome : out  STD_LOGIC_VECTOR (2 downto 0);
           dataword : out  STD_LOGIC_VECTOR (3 downto 0));
end sammy_2018314405;

architecture Behavioral of sammy_2018314405 is

signal s : std_logic_vector(2 downto 0);
signal b3, b2, b1, b0, q2, q1, q0 : std_logic;
signal temp : std_logic_vector(6 downto 0);

begin

b3 <= codeword(6);
b2 <= codeword(5);
b1 <= codeword(4);
b0 <= codeword(3);
q2 <= codeword(2);
q1 <= codeword(1);
q0 <= codeword(0);

s(0) <= b0 xor b1 xor b2 xor q0;
s(1) <= b1 xor b2 xor b3 xor q1;
s(2) <= b0 xor b1 xor b3 xor q2;

temp <= (b3,b2,b1,b0,q2,q1,q0);

process(s)
    begin
        case s is
            when "001" => temp(0) <= not temp(0);
            when "010" => temp(1) <= not temp(1);
            when "011" => temp(5) <= not temp(5);
            when "100" => temp(2) <= not temp(2);
            when "101" => temp(3) <= not temp(3);
            when "110" => temp(6) <= not temp(6);
            when "111" => temp(4) <= not temp(4);
           when others => null;
        end case;
    end process;

syndrome(2 downto 0) <= s(2 downto 0);
dataword(3 downto 0) <= temp(6 downto 3);

end Behavioral;

--我收到警告，显示 temp 应该在进程的敏感性列表中。我不明白这是什么意思。我应该得到如下图所示的结果。

实施结果

标签： vhdlxilinx-ise