vector - 为什么模拟时会得到未定义的输出向量和未定义的时钟？
问题描述
我对 VHDL 很陌生，并且在我的测试平台上遇到了错误（至少我相信它只在测试平台中）。我的程序模拟了一个有 12 个部分的体育场。该程序由 12 个单独的计数器以及达到最大容量的 90% 时的 LED 和一个显示所有 12 个计数器的总数的 4 位数字显示器组成。
每当我尝试编译代码时，任何输出都没有变化，所有输入都未定义。
任何意见，将不胜感激。
建筑学：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_STD.all;
entity counter is
Port (Clk: in STD_LOGIC;
Enable : in STD_LOGIC_Vector(11 downto 0);
Reset : in STD_LOGIC_Vector(11 downto 0);
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12 : out STD_LOGIC_Vector(8 downto 0); -- 9 bits as 300 <2^9
Qt : out STD_LOGIC_Vector(11 downto 0); -- 12 bits as 300 (section) * 12 > 2^12
a,b,c,d,e,f,g : out STD_LOGIC_Vector(3 downto 0); --Individual segments of the display (4 because the number will max out at 3600)
Led0,Led1,Led2,Led3,Led4,Led5,Led6,Led7,Led8,Led9,Led10,Led11 : out STD_LOGIC);
end counter;
Architecture behavioral of counter is
type REG_variable is array(0 to 11) of unsigned(8 downto 0);
type Q_variable is array (0 to 11) of STD_LOGIC_Vector(8 downto 0);
type DIGITS_variable is array (0 to 3) of unsigned (3 downto 0);
signal output_array : Q_variable;
signal LED_Output : STD_LOGIC_Vector(11 downto 0);
component count_comp is
Port(Clk, Reset, Enable : in STD_Logic;
Q : out STD_LOGIC_Vector(8 downto 0);
LED : out STD_LOGIC);
end component;
begin
process (CLK,Reset)
variable LED_lights : STD_LOGIC_Vector(11 downto 0) := (others => '0');
variable REG : REG_variable := (others =>(others => '0'));
variable Total_REG: unsigned(11 downto 0) := (others => '0');
variable Digits : DIGITS_variable := (others => (others => '0'));
begin
Single_Counter : for i in 11 downto 0 loop
if Reset(i) = '1' then
Total_REG := Total_REG - REG(i);
REG(i) := (others => '0');
LED_lights(i) := '0';
elsif rising_edge(CLK) then
if Enable(i) = '1' and (REG(i) <= 300) then
if (REG(i) >= 270) then
LED_lights(i) := '1';
Total_REG := Total_REG + 1;
REG(i) := REG(i)+ 1;
end if;
Digits(0) := to_unsigned(to_integer(Total_REG - Total_REG mod 100),4);
Digits(1) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/10),4);
Digits(2) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/100),4);
Digits(3) := to_unsigned(to_integer((Total_REG - Total_REG mod 100)/1000),4);
end if;
end if;
Qt <= STD_LOGIC_Vector(Total_REG);
output_array(i) <= STD_LOGIC_Vector(REG(i));
LED_output(i) <= LED_lights(i);
for x in 3 downto 0 loop
case to_integer(Digits(x)) is
when 0
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '1'; d(x) <= '1'; e(x) <= '1'; f(x) <= '1'; g(x) <= '0';
when 1
=> a(x) <= '0'; b(x) <= '1'; c(x) <= '1'; d(x) <= '0'; e(x) <= '0'; f(x) <= '0'; g(x) <= '0';
when 2
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '0'; d(x) <= '1'; e(x) <= '1'; f(x) <= '0'; g(x) <= '1';
when 3
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '1'; d(x) <= '1'; e(x) <= '0'; f(x) <= '0'; g(x) <= '1';
when 4
=> a(x) <= '0'; b(x) <= '1'; c(x) <= '1'; d(x) <= '0'; e(x) <= '0'; f(x) <= '1'; g(x) <= '1';
when 5
=> a(x) <= '1'; b(x) <= '0'; c(x) <= '1'; d(x) <= '1'; e(x) <= '0'; f(x) <= '1'; g(x) <= '1';
when 6
=> a(x) <= '1'; b(x) <= '0'; c(x) <= '1'; d(x) <= '1'; e(x) <= '1'; f(x) <= '1'; g(x) <= '1';
when 7
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '1'; d(x) <= '0'; e(x) <= '0'; f(x) <= '0'; g(x) <= '0';
when 8
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '1'; d(x) <= '1'; e(x) <= '1'; f(x) <= '1'; g(x) <= '1';
when 9
=> a(x) <= '1'; b(x) <= '1'; c(x) <= '1'; d(x) <= '1'; e(x) <= '0'; f(x) <= '1'; g(x) <= '1';
when others
=> a(x) <= '0'; b(x) <= '0'; c(x) <= '0'; d(x) <= '0'; e(x) <= '0'; f(x) <= '0'; g(x) <= '0';
end case;
end loop;
end loop;
end process;
Counters : for i in 11 downto 0 generate
counter_gen : count_comp
port map (CLK => CLK, Reset => Reset (i), Enable => Enable(i), Q => output_array(i), LED => LED_output(i));
end generate;
Q1 <= output_array(0);
Q2 <= output_array(1);
Q3 <= output_array(2);
Q4 <= output_array(3);
Q5 <= output_array(4);
Q6 <= output_array(5);
Q7 <= output_array(6);
Q8 <= output_array(7);
Q9 <= output_array(8);
Q10 <= output_array(9);
Q11 <= output_array(10);
Q12 <= output_array(11);
Led0 <= LED_output(0);
Led1 <= LED_output(1);
Led2 <= LED_output(2);
Led3 <= LED_output(3);
Led4 <= LED_output(4);
Led5 <= LED_output(5);
Led6 <= LED_output(6);
Led7 <= LED_output(7);
Led8 <= LED_output(8);
Led9 <= LED_output(9);
Led10 <= LED_output(10);
Led11 <= LED_output(11);
end behavioral;
试验台：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Project_Testbench is
end;
architecture TB1 of Project_Testbench is
component count_comp is
Port(Clk: in STD_LOGIC;
Enable : in STD_LOGIC_Vector(11 downto 0);
Reset : in STD_LOGIC_Vector(11 downto 0);
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12 : out STD_LOGIC_Vector(8 downto 0);
Qt : out STD_LOGIC_Vector(11 downto 0);
a,b,c,d,e,f,g : out STD_LOGIC_Vector(3 downto 0);
Led0,Led1,Led2,Led3,Led4,Led5,Led6,Led7,Led8,Led9,Led10,Led11 : out STD_LOGIC);
end component count_comp;
signal Clk_TB : std_logic := '0';
signal Enable : std_logic_Vector(11 downto 0) := (others => '0');
signal Reset : std_logic_Vector(11 downto 0) := (others => '0');
begin
Clk_TB <= not Clk_TB after 5ns;
stimuli: process
begin
Enable <= "000000000000"; Reset <= "11111111111";
wait for 100 ns;
Enable <= "11111111111"; Reset <= "00000000000";
wait for 200 ns;
Enable <= "11110011111"; Reset <= "00000000000";
wait for 50 ns;
Enable <= "00011111111"; Reset <= "00000000000";
wait for 20 ns;
Enable <= "11111111111"; Reset <= "11000000000";
wait for 20 ns;
Enable <= "11111111111"; Reset <= "00000000000";
wait for 1000 ns;
wait;
end process;
uut: count_comp port map
(
Clk => Clk_TB,
Enable => Enable,
Reset => Reset);
end;
这是输出信号的屏幕截图。 输出信号
解决方案
推荐阅读
- machine-learning - 我们丢弃变量的缺失值百分比是多少（我有一个缺失值为 21% 的变量）？
- mysql - 如何使用 MAMP 在 CakePHP 中修复与数据库的连接
- c - 即使输入正确，if 语句也始终为真？
- android - 在释放模式下按下 home 键后重新打开 loginActivity
- firebase - yarn add firebase 给出“未满足的对等依赖”警告
- linux - 使用 Sed 删除空格
- sql - 通过 html 格式的电子邮件发送子查询结果
- python - 我如何在数组概念中打印 2 个或更多值
- c++ - C++ 等价于 Fortran Namelist
- python - 在python中导出excel或csv文件时删除第一列