fpga - Xilinx Mircrozed 在 QSPI 启动模式错误上加载新比特流

Question

在 Xilinx Microzed 板上以 QSPI 模式加载我的 bistream 时失败；

QSPI 模式由 uboot 提示符上的 qspimode var 定义

zynq-uboot> printenv qspiboot

qspiboot= 
sf probe 0 0 0 && 
sf read ${loadbit_addr} 0xC00000 ${bitstream_size} && 
mw 0xF8007080 0x30800100 0x4 && 
fpga load 0 ${loadbit_addr} ${bitstream_size} && 
sf read 0x3000000 0x100000 ${kernel_size} && 
sf read 0x2A00000 0x600000 ${devicetree_size} && 
sf read 0x2000000 0x620000 ${ramdisk_size} && 
bootm 0x3000000 0x2000000 0x2A00000

也可以直接从 SD 而不是 QSPI 存储器加载比特流。

SD和QSPI模式的区别在于PCAP寄存器0xF8007080这一行，网上没有更多信息；我尝试阅读 Xilinx 文档以获取信息；

在 SD 启动时，比特流的启动命令没有问题，也没有“mw”：

Zynq> fatload mmc 0 ${loadbit_addr} ${bitstream_image}
reading bitstream.bin
4045564 bytes read in 357 ms (10.8 MiB/s)

Zynq>  fpga load 0 ${loadbit_addr} ${filesize}
zynq_align_dma_buffer: Bitstream is not swapped(1) - swap it

之后：蓝色 LED OK：bitstrem 已加载

Zynq> printenv loadbit_addr bitstream_image filesize

loadbit_addr=0x100000
bitstream_image=bitstream.bin
filesize=3dbafc

问题是 QSPI 模式：

zynq-uboot> fatls mmc 0
  3654352   uimage
     2232   uenv.txt
   473380   u-boot.bin
   473444   u-boot.img
    86340   boot.bin
  4045564   bitstream.bin
  1048576   mtd0-qspi-fsbl-uboot
  5242880   mtd1-qspi-linux
   131072   mtd2-qspi-device-tree
  6160384   mtd3-qspi-rootfs
      182   mtd_save.sh
     1635   readme
    68141   config.usine.gz
      495   update_qspi.sh
   868364   busybox

zynq-uboot> fatload mmc 0 ${loadbit_addr} ${bitstream_image}
reading bitstream.bin
4045564 bytes read in 551 ms (7 MiB/s)

zynq-uboot> mw 0xF8007080 0x30800100 0x4

zynq-uboot> fpga load 0 ${loadbit_addr} ${filesize}
Error: Timeout waiting for FPGA to config.
fpga - loadable FPGA image support

Usage:
fpga [operation type] [device number] [image address] [image size]
fpga operations:
  dump  [dev]                   Load device to memory buffer
  info  [dev]                   list known device information
  load  [dev] [address] [size]  Load device from memory buffer
  loadb [dev] [address] [size]  Load device from bitstream buffer (Xilinx only)
  loadmk [dev] [address]        Load device generated with mkimage
        For loadmk operating on FIT format uImage address must include
        subimage unit name in the form of addr:<subimg_uname>

没有内存写入的相同错误（mr）

zynq-uboot> fatload mmc 0 ${loadbit_addr} ${bitstream_image}
reading bitstream.bin
4045564 bytes read in 551 ms (7 MiB/s)

zynq-uboot> fpga load 0 ${loadbit_addr} ${filesize}
Error: Timeout waiting for FPGA to config.
fpga - loadable FPGA image support

Usage:
fpga [operation type] [device number] [image address] [image size]
fpga operations:
  dump  [dev]                   Load device to memory buffer
  info  [dev]                   list known device information
  load  [dev] [address] [size]  Load device from memory buffer
  loadb [dev] [address] [size]  Load device from bitstream buffer (Xilinx only)
  loadmk [dev] [address]        Load device generated with mkimage
        For loadmk operating on FIT format uImage address must include
        subimage unit name in the form of addr:<subimg_uname>

这与 Web 链接上的 ISSUE 相同，即“错误：超时等待 FPGA 配置”；

我尝试使用 bitstream.bit 和一个简单的 bif 文件生成 bitstream.bit：

all :
{
bitstream.bit
}

bootgen -image bitstream.bif -o bitstream.bin -w 

stef@srv:fpga_zynq.runs.impl_1$ bootgen -image bitstream.bif -o bitstream.bin -w


****** Xilinx Bootgen v2020.3
  **** Build date : Apr  6 2021-16:53:00
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully

stef@POC:fpga_zynq.AE3666_HW01.runs.impl_1$ ls -lrt bit*
-rw-r--r-- 1 stef stef 4045686 Apr  8 12:57 bitstream.bit
-rw-r--r-- 1 stef stef      25 Apr  8 12:57 bitstream.bif
-rw-r--r-- 1 stef stef 4051456 Apr  8 12:57 bitstream.bin

但没有变化

什么问题？？

这个问题只涉及比特流；使用内核或设备树刷新、加载和引导不会显示问题；

感谢您的帮助；

史蒂文

标签： fpgaxilinx