cpu-architecture - 确定 CPU 中寄存器的值

Question

在此处输入图像描述 在特定时钟周期内，考虑图中所示的 CPU。
假设存在以下初始数据（所有值均以十进制显示）：
x3=72、x4=40、x8=0、x16=24、x17=56、x18=48、x20=40、x24=80
假设以下五条指令在流水线中
（第一列是指令的地址；所有值都以十进制显示）：
66992 beq x17,x16,24
66996 addi x17,x8,8
67000 sd x20,40(x24)
67004 sub x10 ,x4,x18
67008 ori x27,x3,16
在有问题的循环中，上表第一行的指令处于
回写阶段，上表最后一行的指令处于取指阶段
阶段。
如何确定 L1 、 L2 和 L3 的值？：

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我不知道如何开始解决这类问题。就像 L1 是关于
读取数据 1。但是它将从哪里读取数据。似乎
L1 连接到指令 [31-0]、指令 [30,14-12] 和
指令 [11-7]。所以它会从这条指令之一读取数据如果我考虑到在指令获取阶段
的事实，那么 L1 应该包含 x3 = 72 的值 不确定这是否正确or x21,x3,x19

标签： cpu-architectureriscv

Answer 1

The lines: Read register 1, Read register 2, Write register are all 5-bit lines that are register names (numbers) coming from fields of the instruction.  Write data is a 64-bit lined that comes from an earlier instruction (later in the diagram).

You have to know some of the basics of decoding in the processor and what each instruction does to know this.

Unfortunately, your diagram is seriously abstract — in particular, the line L2, for example, is not labeled.

Have a look at this article explaining some things about timing: https://www.codementor.io/@erikeidt/logic-block-diagrams-w6zxr6sp6.  Of particular note, the instruction fields that feed Read register 1, and 2 and Write register are labeled with instruction field bit positions that you can relate to the RISC V instruction formats in an presentation such as this: https://inst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture7.pdf (see slide 8 for an overview of the formats).

These two pieces of information, put together, tell us that Read register 2, for example, comes from instruction field 24:20, which corresponds to what is known as the rs2 field of R-Type, S-Type and SB-type instructions.

It is a bit of a leap, but the corresponding value on L1 is the 64-bit (assuming RV64) value looked up in the Registers (register file) found in the register named by L2 (at the time that lookup is executed).

So, if you know a little bit about how the I-Type instruction, for example, works differently from an R-Type instruction, that will inform you as to what is on some of these datapaths.

L3 is the ALU comparator output, which on some processor designs is output on the EX stage to indicate whether two registers compare for equality or not, and used by conditional branch instructions (beq and bne).

These diagrams are all woefully abstract from what actually has to happen in the hardware, as RISC V has many more conditional branches than == and !=, but many of these diagrams are adapted from the original MIPS, which only had those two comparators for conditional branching.

L4 is a new PC value, used when a conditional branch is taken.

L5, hard to see in this diagram, but is the ALU output forwarded to some MUXes that choose what value for Write data.

(Your diagram also includes pipeline registers & stages, many other's don't and certain details are easier to understand on the corresponding single cycle diagram.)

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Yes, for that ori with register x3, L2 would be 3 (for x3) and L1 would be 72.