vhdl - 为什么这个 vhdl 代码会陷入无限循环?
问题描述
我正在学习 vhdl 并为 T Flip-Flop 编写了以下代码,但它陷入了无限循环。编译时我发现 q 和 q bar 将是相同的,所以我想这就是原因,但我不知道如何解决这个问题。
我的 TFF.vhd :
library IEEE;
use IEEE.std_logic_1164.all;
entity TFF is
port (
t : in bit;
clk : in bit;
q : out bit;
q_bar : out bit
);
end entity TFF;
architecture structrial of TFF is
signal t_q_bar,t_q,t1,t2: bit;
begin
t1 <= (t and t_q ) and clk ;
t2 <=(t and t_q_bar) and clk;
t_q <= t1 nor t_q_bar;
t_q_bar <= t2 nor t_q;
q <= t_q;
q_bar <= t_q_bar ;
end structrial;
我的测试台:
library IEEE;
use IEEE.std_logic_1164.all;
entity TFF_test is
--nothing
end entity TFF_test;
architecture test of TFF_test is
component TFF is
port (
t : in bit;
clk : in bit ;
q : out bit;
q_bar : out bit
);
end component;
for all : TFF use entity work.TFF(structrial);
signal t_temp :bit;
signal q_temp :bit;
signal q_bar_temp :bit;
signal clk_temp:bit:='0';
begin
uut : TFF port map (t_temp,clk_temp,q_temp,q_bar_temp);
clk_temp <= not clk_temp after 5 ns;
t_temp <= '1' after 10 ns ,'0' after 20 ns , '1' after 30 ns , '0' after 50 ns;
end architecture test;