vhdl - 信号countris不能合成，同步描述不好

Question

        entity T3 is
                Port ( clk : in  STD_LOGIC;
                          rise : out integer range 0 to 10;
                          fall : out integer range 0 to 10);
                          
            end T3;
            
            architecture Behavioral of T3 is
            --assigning signals to count falling and rising edge
            signal countfal:  integer range 0 to 10 :=0;
            signal countris:  integer range 0 to 10 :=0; --rising edge 
             
            begin
            process(clk) 
            begin
            --count upto 10 clocks
            for i in 0 to 10 loop
            if (falling_edge(clk)) then countfal<= countfal+1;
            elsif(rising_edge(clk))  then countris<= countris+1;
            end if;
            end loop;
            -- Output both counters 
            rise<=countris; 
            fall<=countfal; 
            end process;
            end Behavioral;

*** 我正在尝试计算时钟的上升沿和下降沿，但出现此错误信号计数无法合成，同步描述错误。***

标签： vhdl