verilog - How to eliminate Verilog instance syntax error

Question

This code is of 4:1 mux from three 2:1 muxes, and I am getting this syntax error. How do I eliminate this error?

ERROR:HDLCompiler:806 - "D:\Verilog\muxx\mux4.v" Line 12: Syntax error near "[".
ERROR:HDLCompiler:806 - "D:\Verilog\muxx\mux4.v" Line 13: Syntax error near "[".
ERROR:HDLCompiler:806 - "D:\Verilog\muxx\mux4.v" Line 14: Syntax error near "[".

---

module fmux(

input [3:0] a,
input [1:0] s,
output o
);
wire x,y;


 muxx m0(.a[0](a[0]), .a[1](a[1]), .s(s[0]), .o(x));    //error
 muxx m1(.a[0](a[2]), .a[1](a[3]), .s(s[0]), .o(y));   //error
 muxx m2(.a[0](x), .a[1](y), .s(s[1]), .o(o));        //error

endmodule

标签： verilog

Answer 1

语法错误指向.a[0].

假设您的muxx端口如下所示，那么您可以按如下方式进行连接：

module muxx (
    input [1:0] a,
    input s,
    output o
);
endmodule

module fmux (
    input [3:0] a,
    input [1:0] s,
    output o
);
    wire x,y;

    muxx m0 (.a(a[1:0]), .s(s[0]), .o(x));
    muxx m1 (.a(a[3:2]), .s(s[0]), .o(y));
    muxx m2 (.a({y, x}), .s(s[1]), .o(o)); 
endmodule