vhdl - Intel Quartus 错误 12002 端口在宏功能中不存在

Question

使用 Intel Cyclone 10 FPGA 并遇到编译错误，我似乎无法正确调试。我得到的错误是：

Error (12002): Port "out_msg" does not exist in macrofunction "inst6"
Error (12002): Port "msg" does not exist in macrofunction "inst5"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 68 warnings
    Error: Peak virtual memory: 4803 megabytes
    Error: Processing ended: Wed Jan 06 09:42:35 2021
    Error: Elapsed time: 00:00:09
    Error: Total CPU time (on all processors): 00:00:19
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 68 warnings

我相信这两个错误是同一个问题。 这是相关的 .bdf 布局图像

这是“inst6”块中的代码，是导致第一个错误的代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;               -- Needed for shifts
use work.can;

entity can_pack is
  port(
    clk              : in  std_ulogic;
    rst              : in  std_ulogic;
    enbl             : in  std_ulogic;
     data_in         : in  std_logic_vector(7 downto 0);
     data_in1        : in  std_logic_vector(7 downto 0);
     data_in2        : in  std_logic_vector(7 downto 0);
     data_in3        : in  std_logic_vector(7 downto 0);
     data_in4        : in  std_logic_vector(7 downto 0);
     data_in5        : in  std_logic_vector(7 downto 0);
     data_in6        : in  std_logic_vector(7 downto 0);
     data_in7        : in  std_logic_vector(7 downto 0);
     out_msg         : out work.can.message;
     ready_out       : out std_ulogic;
    tx               : inout std_ulogic);
end can_pack;

architecture syn of can_pack is

  signal ready              : std_ulogic;
  signal msg                    : work.can.message;
  
begin
  
  process(clk, rst, data_in)

  begin
      msg.id  <= x"355"; --NOTE: With ID defined to be 12 bits, please be mindfull that you don't set the ID to be >0x7FF
      msg.len <= x"8";
      msg.dat(63 downto 56) <= data_in;
      msg.dat(55 downto 48) <= data_in1;
      msg.dat(47 downto 40) <= data_in2;
      msg.dat(39 downto 32) <= data_in3;
      msg.dat(31 downto 24) <= data_in4;
      msg.dat(23 downto 16) <= data_in5;
      msg.dat(15 downto  8) <= data_in6;
      msg.dat(7  downto  0) <= data_in7;
      out_msg <= msg;

  if rst = '1' then
    ready <= '0';
  elsif rising_edge(clk) then

    --enbl is the clock rate for message broadcast
    if enbl = '0' then
        ready <= '1';
        ready_out <= '1';
    elsif enbl = '1' then   --not sure if this is the right way to do this
        ready <= '0';
        ready_out <= '0';
     end if;
   end if;
  end process;   
end syn;

我相信这个问题与被设置为输出的定义类型的数据有关。inst5 的输入采用相同的类型。当我将 out_msg 的类型更改为 std_ulogic 时，代码编译没有问题。

这是 out_msg 数据类型的定义记录：

library ieee;
use ieee.std_logic_1164.all;

package can is
  type message is record
    id  : std_ulogic_vector(11 downto 0);
    len : std_ulogic_vector(3 downto 0);
    dat : std_logic_vector(63 downto 0);
  end record message;
end package can;

package body can is
end package body can;

我对 VHDL 和 Quartus 等还是很陌生，所以我可能会遗漏一些明显的东西。但感谢您的帮助。

标签： vhdlintelfpgacan-busquartus