vhdl - VHDL输出信号给出UUUUUUU

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity carry_select is
generic(
    N_BIT   : integer range 2 to 32 := 3; -- Number of bits per operand.
    N_STAGE : integer range 1 to 8  := 2  -- Number of stages for the operands.
);
port(
    op_a        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    op_b        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    carry_in    : in  std_ulogic; 
    res         : out std_ulogic_vector(N_BIT     downto 0)
);
end entity ; -- carry_select
architecture rtl of carry_select is
-- Divergent Series:
-- https://en.wikipedia.org/wiki/1_%2B_2_%2B_3_%2B_4_%2B_%E2%8B%AF
function n_sum_idx(stage : integer) return integer is
begin 
    return stage * (stage + 1) / 2;
end n_sum_idx;

component ripple_carry_adder is
generic(
    N_BIT : integer range 1 to 16
);
port (
    op_a        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    op_b        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    carry_in    : in  std_ulogic;
    res         : out std_ulogic_vector(N_BIT downto 0)
) ;
end component;

component mux2
    generic(N_BIT : integer range 1 to 32 := 1);
    port(
        sel_in : in  std_ulogic;
        op_a   : in  std_ulogic_vector(N_BIT - 1 downto 0);
        op_b   : in  std_ulogic_vector(N_BIT - 1 downto 0);
        op_out : out std_ulogic_vector(N_BIT - 1 downto 0)
    );
end component mux2;
signal w_sum: std_ulogic_vector(N_BIT-1 downto 0);
signal carry_chain : std_ulogic_vector(N_STAGE downto 0);
begin
-- Implementation goes here!

res(N_BIT)<=carry_chain(4);
res(N_BIT-1 downto 0)<=w_sum;

gen_stage : for i_stage in 0 to N_STAGE - 1 generate
    -- Constant for the start and end address of the current stage.
    -- Applies to the operand and result vectors.
    constant start_idx : integer := n_sum_idx(i_stage);
    constant end_idx : integer := n_sum_idx(i_stage + 1) - 1;
    
    -- Inner variable/signal/constant declaration here!

signal res_out_0,res_out_1: std_ulogic_vector(end_idx +1 downto start_idx);

begin

process( res_out_0,res_out_1, carry_chain, carry_in)
begin
    if(i_stage=0)then
         carry_chain(i_stage)<=carry_in;
        
    elsif(i_stage=1 and carry_chain(i_stage)='0') then
        carry_chain(i_stage)<=res_out_0(end_idx+1);
     elsif (i_stage=1  and carry_chain(i_stage)='1') then
        carry_chain(i_stage)<=res_out_1(end_idx+1);
     elsif (i_stage=2  and carry_chain(i_stage)='0') then
        carry_chain(i_stage)<=res_out_0(end_idx+1);
     elsif (i_stage=2  and carry_chain(i_stage)='1') then
        carry_chain(i_stage)<=res_out_1(end_idx+1);
     elsif (i_stage=3  and carry_chain(i_stage)='0') then
        carry_chain(i_stage)<=res_out_0(end_idx+1);
     elsif (i_stage=3  and carry_chain(i_stage)='1') then
        carry_chain(i_stage)<=res_out_1(end_idx+1);
     elsif (i_stage=4  and carry_chain(i_stage)='0') then
        carry_chain(i_stage)<=res_out_0(end_idx+1);
     elsif (i_stage=4  and carry_chain(i_stage)='1') then
        carry_chain(i_stage)<=res_out_1(end_idx+1);
    end if;
    end process;
        


    -- Generate RCA here.
rca_instance_0: ripple_carry_adder

    generic map(
        N_BIT => i_stage+1
    )
port map (
op_a => op_a(end_idx downto start_idx),
op_b => op_b(end_idx downto start_idx),
carry_in => '0',
res => res_out_0(end_idx+1 downto start_idx)
);

rca_instance_1: ripple_carry_adder
generic map(N_BIT =>  i_stage+1)
port map (
op_a => op_a(end_idx downto start_idx),
op_b => op_b(end_idx downto start_idx),
carry_in => '1',
res => res_out_1(end_idx+1 downto start_idx)
);

mux_instance: mux2
generic map(N_BIT => i_stage+1)
port map(
sel_in => carry_chain(i_stage),
op_a => res_out_0(end_idx downto start_idx),
op_b => res_out_1(end_idx downto start_idx),
op_out => w_sum(end_idx downto start_idx)
);


    
end generate;

end architecture ; -- rtl

---

-- 多路复用器2

entity mux2 is
generic (
N_BIT : integer range 1 to 32 := 1  -- Number of bits per operand.
);
port (
sel_in : in  std_ulogic; -- Select signal
op_a   : in  std_ulogic_vector(N_BIT - 1 downto 0); 
op_b   : in  std_ulogic_vector(N_BIT - 1 downto 0); 
op_out : out std_ulogic_vector(N_BIT - 1 downto 0)
) ;
end entity ; -- mux2

architecture rtl of mux2 is
begin
-- Implement multiplexer here!
process(op_a,op_b,sel_in)
begin
if sel_in = '0' then
op_out <= op_b ;
else 
op_out <= op_a;
end if;
end process;
end architecture ; -- rtl

---

- 试验台

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_tb is
-- Testbench
end entity ; -- adder_tb

architecture sim of adder_tb is
constant N_BIT   : integer := 10; -- Number of bits for the CSCA and CSA
constant N_STAGE : integer := 4; -- Number of stages for the CSCA

component carry_select is
generic(
    N_BIT   : integer range 2 to 32 := 3; -- Number of bits per operand.
    N_STAGE : integer range 1 to 8  := 2  -- Number of stages for the operands.
);
port(
    op_a        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    op_b        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    carry_in    : in  std_ulogic;
    res         : out std_ulogic_vector(N_BIT     downto 0)
);
end component ; -- carry_select

component cond_sum is
generic(
    N_BIT : integer range 2 to 32 := 3 -- Number of bits per operand.
);
port(
    op_a        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    op_b        : in  std_ulogic_vector(N_BIT - 1 downto 0);
    carry_in    : in  std_ulogic;
    res         : out std_ulogic_vector(N_BIT     downto 0)
);
end component;

-- Input/Output signals.
signal op_a     : std_ulogic_vector(N_BIT - 1 downto 0);
signal op_b     : std_ulogic_vector(N_BIT - 1 downto 0);
signal carry_in : std_ulogic;
signal res_csca : std_ulogic_vector(N_BIT downto 0); 
signal res_csa  : std_ulogic_vector(N_BIT downto 0); 
begin

---

-- Full-Adder 和 Ripple-Carry-Adder 的测试过程。

test : process
begin

    -------------------------------------------------------------------------
    -- Test for Carry-Select-Adder.
    -------------------------------------------------------------------------
    -- Test 1: All zero test with zero carry: 0 + 0 + 0 = 0
    op_a <= (others => '0');
    op_b <= (others => '0');
    carry_in <= '0';
    wait for 10 ns;
    
    assert res_csca = std_ulogic_vector(to_unsigned(0, res_csca'length))
    report "Carry-Select Test 1: Failed"
    severity error;
    report "Carry-Select Test 1: Done";
    wait for 10 ns;

    -- Test 2: All zero test with one carry: 0 + 0 + 1 = 1
    op_a <= (others => '0');
    op_b <= (others => '0');
    carry_in <= '1';
    wait for 10 ns;
    
    assert res_csca = std_ulogic_vector(to_unsigned(1, res_csca'length))
    report "Carry-Select Test 2: Failed"
    severity error;
    report "Carry-Select Test 2: Done";
    wait for 10 ns;

    -- Test 3: Max value test with zero carry: 1023 + 1023 = 2046
    op_a <= (others => '1');
    op_b <= (others => '1');
    carry_in <= '0';
    wait for 10 ns;
    
    assert res_csca = std_ulogic_vector(to_unsigned(2046, res_csca'length))
    report "Carry-Select Test 3: Failed"
    severity error;
    report "Carry-Select Test 3: Done";
    wait for 10 ns;

     -- Test 4: Max value test with zero carry: 1023 + 1023 + 1 = 2047
    op_a <= (others => '1');
    op_b <= (others => '1');
    carry_in <= '1';
    wait for 10 ns;
    
    assert res_csca = std_ulogic_vector(to_unsigned(2047, res_csca'length))
    report "Carry-Select Test 4: Failed"
    severity error;
    report "Carry-Select Test 4: Done";
    wait for 10 ns;
    -- Instantiation of the Carry Select adder.
    dut_csca : carry_select
    generic map(
    N_BIT => N_BIT,
    N_STAGE => N_STAGE
)
    port map(
    op_a => op_a,
    op_b => op_b,
    carry_in => carry_in,
    res  => res_csca
    );

在模拟中我犯了这个错误我做错了什么似乎我连接了所有东西。如果有人帮助我，我将不胜感激。

错误；
警告：(vsim-8683) 未初始化的输出端口 /adder_tb/dut_csa/res(10 downto 0) 没有驱动程序。该端口将为信号网络贡献价值（UUUUUUUUUUU）。

标签： vhdl